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參數(shù)資料
| 型號(hào)： | ICS357G-XX |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 200 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封裝： | TSSOP-16 |
| 文件頁(yè)數(shù)： | 3/6頁(yè) |
| 文件大?。?/td> | 84K |
| 代理商： | ICS357G-XX |
MDS 357 B
3
Revision 032301
Integrated Circuit Systems, Inc. 525 Race Street San Jose, CA, 95126 (408) 295-9800tel www.icst.com
ICS357
PECL/LVDS Spread Spectrum QTClock
PRELIMINARY INFORMATION
External Components / Crystal Selection
The ICS357 requires a 0.01F decoupling capacitor to be connected between VDD and GND on pins 5 and 6, and
another between pins 12 and 11. These must be connected close to the ICS357 to minimize lead inductance. No
other external power supply filtering is required for this device, but a large tantalum capacitor of 2.2 to 10 F will
reduce the output jitter in noisy environments. The outputs should be connected to a resistor divider network, as
indicated on the block diagram, and a resistor should be connected from pin RES to VDD. All of these resistor
values can be determined from our application note MAN09. For a crystal input, a parallel resonant, fundamental
mode crystal should be used. Crystal capacitors must be connected from each of the pins X1 and X2 to Ground.
The value (in pF) of these crystal caps should equal (CL-6pf)*2, where CL is the crystal load capacitance in pF. As an
example, for a crystal with 16 pF load capacitance, each crystal capacitor would be 20 pF [(16 - 6pf)*2 = 20].
For a clock input, connect to X1/ICLK and leave X2 unconnected (no capacitors on either X1 or X2).
Device Configuration
The ICS357 QTClock can be programmed for up to 8 input/output frequency combinations, or spread amounts. All
chip functions are controlled from an OTP ROM which has 3 input control lines (S2, S1, S0). Each address location
gives control of the following:
1) Multiplier ratios can be selected.
2) The spread spectrum function can be enabled or disabled.
3) The spread amount can be selected.
The specification is complete when the ICS357 QTClock Order Form accompanies this data sheet. The order form
lists the input and CLK actual frequencies, as well as any other available options. This unique configuration is given
a two character alphanumeric programming code (ICS357-xx), which must be specified when referring to samples.
相關(guān)PDF資料 |
PDF描述 |
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| ICS357M-XXT | 200 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| ICS357M-XXT-LF | 200 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| ICS357M-XX | 200 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| ICS357M-XX-LF | 200 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| ICS357G-XX-LF | 200 MHz, OTHER CLOCK GENERATOR, PDSO16 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS3726-02 | 制造商:ICS 制造商全稱:ICS 功能描述:HIGH PERFORMANCE VCXO |
| ICS3726-12 | 制造商:ICS 制造商全稱:ICS 功能描述:HIGH PERFORMANCE VCXO |
| ICS3726M-02 | 制造商:ICS 制造商全稱:ICS 功能描述:HIGH PERFORMANCE VCXO |
| ICS3726M-02LF | 功能描述:IC VCXO 24-36MHZ 12MA TTL 8-SOIC RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| ICS3726M-02LFT | 功能描述:IC VCXO HI PERF 8-SOIC RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無(wú) 頻率 - 最大:240MHz 除法器/乘法器:是/無(wú) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
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