參數(shù)資料
型號: ICS357M-XX-LF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 200 MHz, OTHER CLOCK GENERATOR, PDSO16
封裝: SOIC-16
文件頁數(shù): 2/6頁
文件大?。?/td> 84K
代理商: ICS357M-XX-LF
MDS 357 B
2
Revision 032301
Integrated Circuit Systems, Inc. 525 Race Street San Jose, CA, 95126 (408) 295-9800tel www.icst.com
ICS357
PECL/LVDS Spread Spectrum QTClock
PRELIMINARY INFORMATION
Pin Assignment
Number
Name
Type Description
1
X1/ICLK
XI
Crystal connection. Connect to fundamental mode crystal or clock input.
2
S0
I
Select pin 0 for frequency table/chip control. Internal pull-up resistor.
3
S1
I
Select pin 1 for frequency table/chip control. Internal pull-up resistor.
4
REFOUT
O
Buffered crystal oscillator (or input reference clock) output. Note 1.
5
VDD
P
Connect to +3.3V or +5V. Must be same voltage as pins 12 and 15.
6
GND
P
Connect to ground.
7
NC
-
No Connect. Do not connect anything to this pin.
8
RES
-
External resistor for setting common mode.
9
PECL
O
Differential clock output. Can be PECL or LVDS. See app note MAN09.
10
PECL
O
Differential clock output. Can be PECL or LVDS. See app note MAN09.
11
GND
P
Connect to ground.
12
VDD
P
Connect to +3.3V or +5V. Must be same voltage as pins 5 and 15.
13
S2
I
Select pin 2 for frequency table/chip control. Internal pull-up resistor.
14
PDTS
I
All-chip Power Down when low. Internal pull-up resistor.
15
VDD
P
Connect to +3.3V or +5V. Must be same voltage as pins 5 and 12.
16
X2
XO
Crystal connection. Leave unconnected for clock input.
Pin Descriptions
Key: XI, XO = crystal connections, I = Input, O = output, P = power supply connection
Note 1: This is a CMOS (rail-to-rail) output clock. For less noise on PECL clocks, program this output to the
off state.
1
12
2
3
4
11
10
9
REFOUT
S0
VDD
16 pin TSSOP or SOIC
5
6
7
8
VDD
S1
X1/ICLK
X2
S2
RES
NC
14
13
15
16
GND
VDD
PECL
GND
PDTS
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PDF描述
ICS357M-XX 200 MHz, OTHER CLOCK GENERATOR, PDSO16
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