參數(shù)資料
型號: ICS408MLFT
元件分類: 時鐘產(chǎn)生/分配
英文描述: 80 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO8
封裝: 0.150 INCH, SOIC-8
文件頁數(shù): 3/6頁
文件大?。?/td> 66K
代理商: ICS408MLFT
PC PERIPHERAL CLOCK
MDS 408 B
3
Revision 032602
Integrated Circuit Systems, Inc. q 525 Race Street, San Jose, CA 95126 q tel (408) 295-9800 q
www.icst.com
ICS408
been the crystal and device. Crystal capacitors must be
connected from each of the pins X1 and X1 to ground.
The value (in pF) of these crystal caps should equal
(CL -6pF)*2. In this equation, CL= crystal load
capacitance in pF. Example: For a crystal with a 15 pF
load capacitance, each crystal capacitor would be 18
pF [(15-6) x 2] = 18.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The 0.01F decoupling capacitor should be mounted
on the component side of the board as close to the
VDD pin as possible. No vias should be used between
the decoupling capacitor and VDD pin. The PCB trace
to VDD pin should be kept as short as possible, as
should the PCB trace to the ground via.
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
3) To minimize EMI the 33
series termination resistor,
if needed, should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed
away from the ICS408. This includes signal traces just
underneath the device, or on layers adjacent to the
ground plane layer used by the device.
Selection of 40M/80M Clock
The 40/80M output clock is selected by a soft pull-upp
or pull-down on 40/80M pin (pin 3). On power up, the
rising edge on OE latches, in the high or low level, on
pin 3 which starts the appropriate frequency. Any
low-to-high transistion on OE/LAT after power up will
latch the logic level on pin 3.
相關(guān)PDF資料
PDF描述
ICS408M 80 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO8
ICS408MT 80 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO8
ICS410MLFT 80 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO8
ICS4231M-03 33 MHz, OTHER CLOCK GENERATOR, PDSO8
ICS4231M-03LFT 33 MHz, OTHER CLOCK GENERATOR, PDSO8
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ICS409 制造商:ICS 制造商全稱:ICS 功能描述:PC PERIPHERAL CLOCK
ICS409M 功能描述:IC PC PERIPHERAL CLOCK 8-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器,PLL,頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時鐘倍頻器,零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP(0.173",4.40mm 寬) 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG
ICS409MLF 功能描述:IC PC PERIPHERAL CLOCK 8-SOIC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器,PLL,頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時鐘倍頻器,零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP(0.173",4.40mm 寬) 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG
ICS409MLFT 功能描述:IC PC PERIPHERAL CLOCK 8-SOIC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器,PLL,頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時鐘倍頻器,零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP(0.173",4.40mm 寬) 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG
ICS409MT 功能描述:IC PC PERIPHERAL CLOCK 8-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器,PLL,頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時鐘倍頻器,零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP(0.173",4.40mm 寬) 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG