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參數(shù)資料
| 型號(hào)： | ICS525-01RT |
| 廠商： | MICREL INC |
| 元件分類(lèi)： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 160 MHz, OTHER CLOCK GENERATOR, PDSO28 |
| 封裝： | 0.150 INCH, SSOP-28 |
| 文件頁(yè)數(shù)： | 4/5頁(yè) |
| 文件大?。?/td> | 79K |
| 代理商： | ICS525-01RT |
ICS525
OSCaR User Configurable Clock
MDS525E
4
Revision 3098
Printed 5/7/98
MicroClock Division of ICS1271 Parkmoor Ave.San JoseCA95126(408)295-9800tel(408)295-9818fax
ICRO
CLOCK
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)
Supply Voltage, VDD
Referenced to GND
7
V
Inputs
Referenced to GND
-0.5
VDD+0.5
V
Clock Output
Referenced to GND
-0.5
VDD+0.5
V
Ambient Operating Temperature
ICS525-01R
0
70
C
ICS525-01RI
-40
85
C
Soldering Temperature
Max of 10 seconds
260
C
Storage Temperature
-65
150
C
DC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)
Operating Voltage, VDD
3
5.5
V
Input High Voltage, VIH
2
V
Input Low Voltage, VIL
0.8
V
Input High Voltage, VIH, X1/ICLK only
ICLK (Pin 7)
(VDD/2)+1
VDD/2
V
Input Low Voltage, VIL, X1/ICLK only
ICLK (Pin 7)
VDD/2
(VDD/2)-1
V
Output High Voltage, VOH
IOH=-25mA
2.4
V
Output Low Voltage, VOL
IOL=25mA
0.4
V
IDD Operating Supply Current, 15 MHz crystal
No Load, 60MHz out
15
mA
IDD Operating Supply Current, 15 MHz crystal
60MHz out, VDD=3.3V
8
mA
IDD Operating Supply Current, Power Down
PD=0
20
A
IDD Operating Supply Current, Power Down
PD=0, VDD=3.3V
7
A
Short Circuit Current
CLK and REF outputs
±70
mA
On-Chip Pull-up Resistor
V, R, S select, PD pins
270
k
Input Capacitance
V, R, S select, PD pins
4
pF
AC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)
Input Frequency, crystal input
5
27
MHz
Input Frequency, clock input
2
50
MHz
Output Frequency with OD=2, VDD = 4.5 to 5.5V
0 C to 70 C
1
160
MHz
-40 C to +85 C
1
140
MHz
Output Frequency with OD=2, VDD = 3.0 to 3.6V
0 C to 70 C
1
100
MHz
-40 C to +85 C
1
90
MHz
Output Clock Rise Time
0.8 to 2.0V
1
ns
Output Clock Fall Time
2.0 to 0.8V
1
ns
Output Clock Duty Cycle, even output dividers
at VDD/2
45
49 to 51
55
%
Output Clock Duty Cycle, odd output dividers
at VDD/2
40
60
%
Power Down Time, PD low to clocks stopped low
50
ns
Power Up Time, PD high to clocks stable
10
ms
Absolute Clock Period Jitter
Deviation from mean
±90
ps
One Sigma Clock Period Jitter
40
ps
Electrical Specifications
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