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參數(shù)資料
| 型號(hào)： | ICS525-02RILF |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 140 MHz, OTHER CLOCK GENERATOR, PDSO28 |
| 封裝： | 0.150 INCH, SSOP-28 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 76K |
| 代理商： | ICS525-02RILF |
ICS525-01/02
OSCaR User Configurable Clock
MDS525G
4
Revision10209
Printed 11/12/99
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126(408) 295-9800tel www.icst.com
CLK frequency = Input frequency 2
(VDW+8)
(RDW+2)(OD)
Determining (setting) the output frequency
The user has full control in setting the desired output frequency over the range shown in the table on
page 2. To replace a standard oscillator, a user should connect the divider select input pins directly to
ground (or VDD, although this is not required because of internal pull-ups) during Printed Circuit Board
layout, so that the ICS525 automatically produces the correct clock when all components are soldered. It is
also possible to connect the inputs to parallel I/O ports to switch frequencies. By choosing divides
carefully, the number of inputs which need to be changed can be minimized. Observe the restrictions
stated below on allowed values of VDW and RDW.
Also, the following operating ranges should be observed:
10 MHz < Input frequency 2
(VDW+8)
(RDW+2)
< 320 MHz at 5.0V or
< 200 MHz at 3.3V
200 kHz <
Input Frequency
(RDW+2)
Where
Reference Divider Word (RDW) = 1 to 127 (0 is not permitted)
VCO Divider Word (VDW) = 4 to 511 (0, 1, 2, 3 are not permitted)
Output Divider (OD) = values on page 3
See Table on Page 3
for full details of
maximum output.
[
]
ICS525-01 Settings
The output of the ICS525-01 can be determined by the following simple equation:
CLK frequency = Input frequency 2
(VDW+8)
(RDW+2)(OD)
Also, the following operating ranges should be observed:
10 MHz < Input frequency 2
(VDW+8)
(RDW+2)
< TBD MHz at 5.0V or
< TBD MHz at 3.3V
200 kHz <
Input Frequency
(RDW+2)
Where
Reference Divider Word (RDW) = 0 to 127
VCO Divider Word (VDW) = 0 to 511
Output Divider (OD) = values on page 3
See Table on Page 3
for full details of
maximum output.
[
]
ICS525-02 Settings
The output of the ICS525-02 can be determined by the following simple equation:
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS525-02RT | 160 MHz, OTHER CLOCK GENERATOR, PDSO28 |
| ICS525-02RILF | 140 MHz, OTHER CLOCK GENERATOR, PDSO28 |
| ICS525R-02ILF | 250 MHz, OTHER CLOCK GENERATOR, PDSO28 |
| ICS525R-02LFT | 250 MHz, OTHER CLOCK GENERATOR, PDSO28 |
| ICS525R-04ILF | 195 MHz, OTHER CLOCK GENERATOR, PDSO28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS525-03 | 制造商:ICS 制造商全稱:ICS 功能描述:PECL Input OSCaR-TM USER Configurable Clock |
| ICS525-04 | 制造商:ICS 制造商全稱:ICS 功能描述:OSCaR-TM User Configurable PECL Clock |
| ICS5250708 | 制造商:ICS 制造商全稱:ICS 功能描述:LVCMOS User Configurable Clock |
| ICS525-11 | 制造商:ICS 制造商全稱:ICS 功能描述:User Configurable Clock |
| ICS525-12 | 制造商:ICS 制造商全稱:ICS 功能描述:User Configurable Clock |
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