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參數(shù)資料
| 型號： | ICS525-02RILF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 140 MHz, OTHER CLOCK GENERATOR, PDSO28 |
| 封裝： | 0.150 INCH, SSOP-28 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 76K |
| 代理商： | ICS525-02RILF |
ICS525-01/02
OSCaR User Configurable Clock
MDS525G
1
Revision10209
Printed 11/12/99
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126(408) 295-9800tel www.icst.com
Packaged as 28 pin SSOP (150 mil body)
Highly accurate frequency generation
ICS525-01 with output frequencies up to 160 MHz
ICS525-02 with output frequencies up to 200 MHz
User determines the output frequency by
setting all internal dividers
Eliminates need for custom oscillators
No software needed
Pull-ups on all select inputs
Input crystal frequency of 5 - 27 MHz
Input clock frequency of 2 - 50 MHz
Very low jitter
Duty cycle of 45/55 up to 200 MHz
Operating voltages of 3.0 to 5.5V
25mA drive capability at TTL levels
Ideal for oscillator replacement
Industrial temperature versions available
Advanced, low power CMOS process
The ICS525-01 and ICS525-02 OSCaR are
the most flexible way to generate a high quality,
high accuracy, high frequency clock output from
an inexpensive crystal or clock input. The name
OSCaR stands for OSCillator Replacement, as
they are designed to replace crystal oscillators in
almost any electronic system. The user can easily
configure the device to produce nearly any
output frequency from any input frequency by
grounding or floating the select pins. Neither
microcontroller nor software nor device
programmer are needed to set the frequency.
Using Phase-Locked-Loop (PLL) techniques, the
device accepts a standard fundamental mode,
inexpensive crystal to produce output clocks up
to 200 MHz. It can also produce a highly
accurate output clock from a given input clock,
keeping them frequency locked together.
For similar capability with a serial interface, use
the ICS307. For simple multipliers to produce
common frequencies, refer to the LOCO family
of parts, which are smaller and more cost
effective.
Block Diagram
Description
Features
Crystal or
clock input
X1/ICLK
X2
Reference
Divider
Phase Comparator,
Charge Pump,
and Loop Filter
Crystal
Oscillator
VCO
Divider
VCO
Output
Buffer
2
VDD
GND
S2:S0
CLK
Output
Buffer
REF
Output
Divider
R6:R0
V8:V0
2
3
9
7
PD
optional
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS525R-02ILF | 250 MHz, OTHER CLOCK GENERATOR, PDSO28 |
| ICS525R-02LFT | 250 MHz, OTHER CLOCK GENERATOR, PDSO28 |
| ICS525R-04ILF | 195 MHz, OTHER CLOCK GENERATOR, PDSO28 |
| ICS525R-04I | 195 MHz, OTHER CLOCK GENERATOR, PDSO28 |
| ICS525R-04LFT | 200 MHz, OTHER CLOCK GENERATOR, PDSO28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS525-03 | 制造商:ICS 制造商全稱:ICS 功能描述:PECL Input OSCaR-TM USER Configurable Clock |
| ICS525-04 | 制造商:ICS 制造商全稱:ICS 功能描述:OSCaR-TM User Configurable PECL Clock |
| ICS5250708 | 制造商:ICS 制造商全稱:ICS 功能描述:LVCMOS User Configurable Clock |
| ICS525-11 | 制造商:ICS 制造商全稱:ICS 功能描述:User Configurable Clock |
| ICS525-12 | 制造商:ICS 制造商全稱:ICS 功能描述:User Configurable Clock |
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