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參數(shù)資料
| 型號： | ICS525R-04LFT |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 200 MHz, OTHER CLOCK GENERATOR, PDSO28 |
| 封裝： | 0.150 INCH, MO-153, SSOP-28 |
| 文件頁數(shù)： | 4/7頁 |
| 文件大?。?/td> | 149K |
| 代理商： | ICS525R-04LFT |
OSCaRTM User Configurable PECL Clock
MDS 525-04 B
4
Revision 091802
Integrated Circuit Systems, Inc.
● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ● www.icst.com
ICS525-04
External Components
Decoupling Capacitors
As with any high performance mixed-signal IC, the
ICS525-04 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01F must be connected
between each VDD and the GND, one on each side of
the chip.The capacitor must be connected close to the
device to minimize lead inductance. No external power
supply filtering is required for this device.
External Resistors
A 560
resistor must be connected between RES (pin
19) and VDD. A total of four resistors are needed for the
PECL outputs as shown on the block diagram on page
1. The value of these resistors are shown, but can be
varied to change the differential pair output swing and
the common mode voltage. Consult application note
MAN09 for more information.
Crystal Load Capacitors
The total on-chip capacitance for a crystal is
approximately 16 pF, so a parallel resonant,
fundamental mode crystal with this value of load
(correlation) capacitance should be used. For crystals
with a specified load capacitance greater than 16 pF,
crystal capacitors may be connected from each of the
pins X1 and X2 to Ground as shown in the block
diagram. The value (in pF) of these crystal caps should
be (CL - 16)*2, where CL is the crystal load
capacitance. These external capacitors are only
required for applications where the exact frequency is
critical. For a clock input, connect to X1 and leave X2
unconnected (no capacitors on either).
Determining the Output Frequency
Users have full control in setting the desired output
frequency over the range shown in the table on page 2.
To replace a standard oscillator, users should connect
the divider select input pins directly to ground (or VDD,
although this is not required because of internal
pull-ups) during Printed Circuit Board layout. The
ICS525-04 will automatically produce the correct clock
when all components are soldered. It is also possible to
connect the inputs to parallel I/O ports to switch
frequencies. By choosing divides carefully, the number
of inputs which need to be changed can be minimized.
Observe the restrictions on allowed values of VDW and
RDW.
The output of the ICS525-04 can be determined by the
following simple equation:
Where:
Reference Divider Word (RDW) = 0 to 127
VCO Divider Word (VDW) = 0 to 511
Output Divider (OD) = values on page 2
Also, the following operating ranges should be
observed:
See table on page 2 for full details of maximum
output.
The dividers are expressed as integers. For example, if
a 66.66 MHz output on CLK1 is desired from a
14.31818 MHz input, the VCO divider word (VDW)
should be 276, with an output divide (OD) of 2. In this
example, R6:R0 is 0111011, V8:V0 is 100010100 and
S2:S0 is 001. Since all of these inputs have pull-up
resistors, it is only necessary to ground the zero pins,
namely V7, V6, V5, V3, V1, V0, R6, R2, S2, and S1.
To determine the best combination of VCO, reference,
and output divide, use the ICS525 Calculator on our
web site: www.icst.com. The online form is easy to use
and quickly shows you up to three options for these
settings. Alternately, you may send an e-mail to
ics-mk@icst.com.
PECL Frequency
Input Frequency
VDW 8
+
RDW 2
+
() OD
---------------------------------------------
×
=
10M Input Frequency
x VDW 8
+
RDW 2
+
()
----------------------------- 200M 5V
()or162M 3.3v )
()
<<
200kHz InputFrequency
RDW 2
+
()
-----------------------------------------------
<
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相關(guān)代理商/技術(shù)參數(shù) |
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| ICS525R-04T | 功能描述:IC PECL CLK USER CONFIG 28-SSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:OSCaR™ 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| ICS525R-07 | 制造商:ICS 制造商全稱:ICS 功能描述:LVCMOS User Configurable Clock |
| ICS525R-07LF | 制造商:ICS 制造商全稱:ICS 功能描述:LVCMOS User Configurable Clock |
| ICS525R-07LFT | 制造商:ICS 制造商全稱:ICS 功能描述:LVCMOS User Configurable Clock |
| ICS525R-07T | 制造商:ICS 制造商全稱:ICS 功能描述:LVCMOS User Configurable Clock |
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