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參數(shù)資料
| 型號： | ICS525RI-07 |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 250 MHz, OTHER CLOCK GENERATOR, PDSO28 |
| 封裝： | 0.150 INCH, MO-153, SSOP-28 |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 185K |
| 代理商： | ICS525RI-07 |
LVCMOS User Configurable Clock
MDS 525-07/08
B
7
Revision 031706
Integrated Circuit Systems, Inc.
● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS525-07/08
PRELIMINARY INFORMATION
AC Electrical Characteristics
Unless stated otherwise, VDD = 1.8 V to 2.5 V
NOTE 1: Phase relationship between input and output can change at power-up.
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input Frequency
FIN
Crystal input
5
27
MHz
Clock input
2
50
MHz
Output Frequency (ICS525-07)
FOUT
-40 to +85
°C (VDD=2.5)
5
250
MHz
Output Frequency (ICS525-08)
FOUT
-40 to +85
°C (VDD=2.5)
1.2
250
MHz
Output Clock Rise Time
20% to 80% (VDD=2.5)
1
ns
Output Clock Fall Time
80% to 20% (VDD=2.5)
1
ns
Output Frequency (ICS525-07)
FOUT
-40 to +85
°C (VDD=1.8)
5
250
MHz
Output Frequency (ICS525-08)
FOUT
-40 to +85
°C (VDD=1.8)
1.2
250
MHz
Output Clock Rise Time
20% to 80% (VDD=1.8)
1.5
ns
Output Clock Fall Time
80% to 20% (VDD=1.8)
1.5
ns
Output Clock Duty Cycle
at VDD/2
45
49 to 51
55
%
Power-down Time, PD low to
clocks stopped
50
ns
Power-up Time, PD high to
clocks stable
5ms
Absolute Clock Period Jitter,
VDD = 2.5 V
tja
Deviation from mean
ps
One Sigma Clock Period Jitter,
VDD = 2.5 V
tjs
One Sigma
ps
Absolute Clock Period Jitter,
VDD = 1.8 V
tja
Deviation from mean
ps
One Sigma Clock Period Jitter,
VDD = 1.8 V
tjs
One Sigma
ps
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| ICS525RI-07T | 250 MHz, OTHER CLOCK GENERATOR, PDSO28 |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| ICS525RI07LF | 制造商:ICS 制造商全稱:ICS 功能描述:LVCMOS User Configurable Clock |
| ICS525RI-07LF | 制造商:ICS 制造商全稱:ICS 功能描述:LVCMOS User Configurable Clock |
| ICS525RI-07LFT | 制造商:ICS 制造商全稱:ICS 功能描述:LVCMOS User Configurable Clock |
| ICS525RI-07T | 制造商:ICS 制造商全稱:ICS 功能描述:LVCMOS User Configurable Clock |
| ICS525RI-08 | 制造商:ICS 制造商全稱:ICS 功能描述:LVCMOS User Configurable Clock |
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