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參數(shù)資料
| 型號： | ICS542MI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 542 SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封裝： | 0.150 INCH, SOIC-8 |
| 文件頁數(shù)： | 2/6頁 |
| 文件大小： | 166K |
| 代理商： | ICS542MI |
ICS542
CLOCK DIVIDER
IDT / ICS CLOCK DIVIDER
2
ICS542
REV G 122106
Pin Assignment
8-pin (150 mil) SOIC
Clock Decoding Table
0 = connect directly to ground
1 = connect directly to VDD
Pin Descriptions
External Components
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50
trace (a commonly
used trace impedance), place a 33
resistor in series with
the clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20
.
Decoupling Capacitor
As with any high-performance mixed-signal IC, the ICS542
must be isolated from system power supply noise to perform
optimally.
A decoupling capacitor of 0.01F must be connected
between VDD and the PCB ground plane.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) The 0.01F decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
2) To minimize EMI, the 33
series termination resistor (if
needed) should be placed close to the clock output.
3) An optimum layout is one with all components on the
ICLK
VDD
GND
CLK/ 2
S0
OE
S1
CLK
1
2
3
4
8
7
6
5
S1
S0
CLK
CLK/2
00
Power Down All
0
1
Input/6
Input/12
1
0
Input/8
Input/16
1
Input/2
Input/4
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
ICLK
XI
Clock input.
2
VDD
Power
Connect to +3.3 V or +5 V.
3
GND
Power
Connect to ground.
4
S0
Input
Select 0 for output clock. Connect to GND or VDD, per decoding table above.
Internal pull-up resistor.
5
S1
Input
Select 1 for output clock. Connect to GND or VDD, per decoding table above.
Internal pull-up resistor.
6
OE
Input
Output Enable. Tri-states both output clocks when low. Internal pull-up
resistor.
7
CLK/2
Output
Clock output per table above. Low skew divide by two of pin 8 clock.
8
CLK
Output
Clock output per table above.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS542MIT | 542 SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| ICS542MILF | 542 SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| ICS544MI-01LFT | 0.032768 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| ICS544M-01T | 0.032768 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| ICS544MI-01T | 0.032768 MHz, OTHER CLOCK GENERATOR, PDSO8 |
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