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參數(shù)資料
| 型號： | ICS544MI-01T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 0.032768 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| 封裝： | 0.150 INCH, SOIC-8 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 238K |
| 代理商： | ICS544MI-01T |
Clock Divider
MDS 544M-01 A
2
Revision 041505
Integrated Circuit Systems, Inc.
● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS544-01
PRELIM INAR Y INFO RMA T ION
Pin Assignment
8-pin (150 mil) SOIC
Clock Divider Table
0 = connect directly to ground
1 = connect directly to VDD
Pin Descriptions
External Components
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50
trace (a
commonly used trace impedance), place a 33
resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20
.
On chip capacitors- Crystal capacitors should be
connected from pins X1 to ground and X2 to ground to
optimize the initial accuracy. The value (in pf) of these
crystal caps equal (CL-12)*2 in this equation,
CL=crystal load capacitance in pf. For example, for a
crystal with a 16 pF load cap, each external crystal cap
would be 8 pF. [(16-12)x2]=8.
Decoupling Capacitor
As with any high-performance mixed-signal IC, the
ICS544-01 must be isolated from system power supply
noise to perform optimally.
A decoupling capacitor of 0.01F must be connected
between VDD and the PCB ground plane.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The 0.01F decoupling capacitor should be mounted
on the component side of the board as close to the
X1/ICLK
X2
GND
VDD
S0
OE
CLK
S1
1
2
3
4
8
7
6
5
S1
S0
CLK
0
Input/32
0
1
Input/64
10
Input/256
11
Input/512
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
X1/ICLK
XI
Crystal or Clock input.
2
X2
Xo
Connect to crystal for crystal input and leave open for clock input.
3
GND
Power
Connect to ground.
4
S0
Input
Select 0 for output clock. Connect to GND or VDD, per divider table above.
Internal pull-up resistor.
5
CLK
Output
Clock output per table above.
6
OE
Input
Output Enable.Tri-states output clock when low. Also shuts down the oscillator
circuit. Internal pull-up resistor. OE=1 normal operation.
7
VDD
Power
Connect to 2.25 V to 3.6 V.
8
S1
Input
Select 1 for output clock. Connect to GND or VDD, per divider table above.
Internal pull-up resistor.
ICS544-01
Clock Divider
TSD
IDT / ICS Clock Divider
ICS544-01
2
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