參數(shù)資料
型號: ICS556G-03IT
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 25 MHz, OTHER CLOCK GENERATOR, PDSO16
封裝: 4.40 MM, 0.65 MM PITCH, TSSOP-16
文件頁數(shù): 3/8頁
文件大?。?/td> 158K
代理商: ICS556G-03IT
MDS 556-03 B
3
Revision 030204
In te gr ated Circuit Systems 525 Ra ce Street, San Jose, CA 9512 6 tel (4 08) 297-1 201 www.icst.com
Quad LVDS Oscillator/Buffer
ICS556-03
External Component Selection
The ICS556-03 requires a minimum number of external
components for proper operation.
Decoupling Capacitors
A decoupling capacitor of 0.01
F should be connected
between VDD and GND on pins 2 and 10 as close to
the ICS556-03 possible. For optimum device
performance, the decoupling capacitor should be
mounted on the component side of the PCB. Avoid the
use of vias in the decoupling circuit.
LVDS Driver Termination
A general LVDS interface is shown in Figure 2. In a 100
ohm differential transmission line environment, LVDS
drivers require a matched load termination of 100
across near the receiver input. For a multiple LVDS
outputs buffer, if only partial outputs are used, it is
recommended to terminate the un-used outputs.
Quartz Crystal
The ICS556-03, a quad 25 MHz LVDS Clock utilizes an
external crystal to generate 4 pairs of low phase noise
outputs. The crystal should be a fundamental mode,
parallel resonant. Crystal capacitors should be
connected from pins X1 to ground and X2 to ground to
optimize the initial accuracy. The value of these
capacitors is given by the following equation
Crystal Caps (pf)= (CL-12)x2
In the equation, CL is the crystal Load capacitance. So
for the crystal with 16pF load capacitance, two 8
pF[(16-12)x2] capacitors should be used.
The external crystal must be connected as close to the
chip as possible and should be on the same side of the
PCB as the ICS556-03. There should be no via’s
between the crystal pins and the X1 and X2 device
pins. There should be no signal traces underneath or
close to the crystal.
14
D
Output
Differential clock output.
15
EN3
Input
Enable pin for Outputs C and C. EN4 high enables C, C outputs.
EN3 low tri states C, C outputs.No Pull-Up resistor.
16
EN4
Input
Enable pin for Outputs D and D. EN4 high enables D, D outputs.
EN4 low tri states D, D outputs.No Pull-Up resistor.
Pin
Number
Pin
Name
Pin
Type
Pin Description
R1
100 ohm
+
-
2.5V
100 Ohm Differential Transmission Line
LVDS_Driver
Figure 2. Typical LVDS Driver
Termination
相關(guān)PDF資料
PDF描述
ICS556G-03ILF 25 MHz, OTHER CLOCK GENERATOR, PDSO16
ICS556M-04IT OTHER CLOCK GENERATOR, PDSO8
ICS557G-03T 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO16
ICS557GI-03LFT 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO16
ICS557G-03LFT 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO16
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