參數(shù)資料
型號: IDT54FCT162373ETEB
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 總線收發(fā)器
英文描述: FCT SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, CDFP48
封裝: CERPACK-48
文件頁數(shù): 5/7頁
文件大?。?/td> 73K
代理商: IDT54FCT162373ETEB
5
IDT54/74FCT162373AT/CT/ET
FAST CMOS 16-BIT TRANSPARENT LATCH
MILITARYANDINDUSTRIALTEMPERATURERANGES
FCT162373AT
Ind.
Mil.
Symbol
Parameter
Condition(1)
Min.(2)
Max.
Min.(2)
Max.
Unit
tPLH
PropagationDelay
CL = 50pF
1.5
5.2
1.5
5.6
ns
tPHL
xDx to xOx
RL = 500
tPLH
PropagationDelay
2
8.5
2
9.8
ns
tPHL
xLE to xOx
tPZH
OutputEnableTime
1.5
6.5
1.5
7.5
ns
tPZL
tPHZ
OutputDisableTime
1.5
5.5
1.5
6.5
ns
tPLZ
tSU
Set-up Time HIGH or LOW, xDx to xLE
2
2
ns
tH
Hold Time HIGH or LOW, xDx to xLE
1.5
1.5
ns
tW
xLE Pulse Width HIGH
5
6
ns
tSK(o)
OutputSkew(3)
0.5
0.5
ns
FCT162373CT
FCT162373ET
Ind.
Mil.
Ind.
Mil.
Symbol
Parameter
Condition(1)
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max.
Unit
tPLH
PropagationDelay
CL = 50pF
1.5
4.2
1.5
5.1
1.5
3.4
ns
tPHL
xDx to xOx
RL = 500
tPLH
PropagationDelay
2
5.5
2
8
1.5
3.7
ns
tPHL
xLE to xOx
tPZL
OutputEnableTime
1.5
5.5
1.5
6.3
1.5
4.4
ns
tPZH
tPHZ
OutputDisableTime
1.5
5
1.5
5.9
1.5
3.6
ns
tPLZ
tSU
Set-up Time HIGH or LOW, xDx to xLE
2
2
1
ns
tH
Hold Time HIGH or LOW, xDx to xLE
1.5
1.5
1
ns
tW
xLE Pulse Width HIGH
5
6
3(4)
——
ns
tSK(o)
OutputSkew(3)
0.5
0.5
0.5
ns
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This limit is guaranteed but not tested.
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