參數(shù)資料
型號: IDT54FCT162373ETEB
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 總線收發(fā)器
英文描述: FCT SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, CDFP48
封裝: CERPACK-48
文件頁數(shù): 6/7頁
文件大小: 73K
代理商: IDT54FCT162373ETEB
6
MILITARYANDINDUSTRIALTEMPERATURERANGES
IDT54/74FCT162373AT/CT/ET
FAST CMOS 16-BIT TRANSPARENT LATCH
Pulse
G enerator
RT
D.U.T.
V CC
V IN
CL
V OUT
50pF
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHR ONO US C O NTRO L
PRESET
CLEAR
ETC.
SYNCHRO NO US CO NTRO L
tSU
tH
tREM
tSU
tH
PRESET
CLEAR
CLO CK ENABLE
ETC.
HIGH-LOW -HIG H
PULSE
LO W -HIGH-LOW
PULSE
tW
1.5V
SAM E PHASE
INPUT TRANSITIO N
3V
1.5V
0V
1.5V
VOH
tPLH
OUTPUT
O PPO SITE PHASE
INPUT TRANSITIO N
3V
1.5V
0V
tPLH
tPHL
VOL
CONTRO L
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NO RMALLY
LO W
OUTPUT
NO RMALLY
HIG H
SW ITCH
CLOSED
SW ITCH
O PEN
VOL
0.3V
tPLZ
tPZL
tPZH
tPHZ
3.5V
0V
1.5V
ENABLE
DISABLE
VOH
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuits for All Outputs
Enable and Disable Times
Set-up, Hold, and Release Times
Pulse Width
Test
Switch
Open Drain
Disable Low
Closed
Enable Low
All Other Tests
Open
SWITCH POSITION
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate
≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
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