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參數(shù)資料
| 型號(hào)： | IDT5T2110BBI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER TERACLOCK |
| 中文描述： | 5T SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA144 |
| 封裝： | PLASTIC, BGA-144 |
| 文件頁數(shù)： | 14/23頁 |
| 文件大小： | 162K |
| 代理商： | IDT5T2110BBI |
14
INDUSTRIAL TEMPERATURE RANGE
IDT5T2110
2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER TERACLOCK
DC ELECTRICAL CHARACTERISTICS OV ER OPERATING RANGE FOR 1.8V
LVTTL
(1)
Symbol
Parameter
Test Conditions
Input Characteristics
I
IH
Input HIGH Current
V
DD
= 2.7V
I
IL
Input LOW Current
V
DD
= 2.7V
V
IK
Clamp Diode Voltage
V
DD
= 2.3V, I
IN
= -18mA
V
IN
DC Input Voltage
Single-Ended Inputs
(2)
V
IH
DC Input HIGH
V
IL
DC Input LOW
Differential Inputs
V
DIF
DC Differential Voltage
(3,9)
V
CM
DC Common Mode Input Voltage
(4,9)
V
IH
DC Input HIGH
(5,6,9)
V
IL
DC Input LOW
(5,7,9)
V
REF
Single-Ended Reference Voltage
(5,9)
Output Characteristics
V
OH
Output HIGH Voltage
I
OH
= -6mA
I
OH
= -100
μ
A
V
OL
Output LOW Voltage
I
OL
= 6mA
I
OL
= 100
μ
A
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. For 1.8V LVTTL single-ended operation, the RxS pin is MID and
REF
[1:0]
/V
REF
[1:0]
is left floating. If TxS is MID,
FB
/V
REF
2
should be left floating.
3. V
DIF
specifies the mnimuminput differential voltage (V
TR
- V
CP
) required for switching where V
TR
is the "true" input level and V
CP
is the "complement" input level. Differential mode
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching
to a new state.
4. V
CM
specifies the maximumallowable range of (V
TR
+ V
CP
) /2. Differential mode only.
5. For single-ended operation in differential mode,
REF
[1:0]
/V
REF
[1:0]
is tied to the DC voltage V
REF
[1:0]
. The input is guaranteed to toggle within ±200mV of V
REF
[1:0]
when V
REF
[1:0]
is constrained within +600mV and V
DDI
-600mV, where V
DDI
is the nomnal 1.8V power supply of the device driving the REF
[1:0]
input. To guarantee switching in voltage range
specified in the JEDEC 1.8V LVTTL interface specification, V
REF
[1:0]
must be maintained at 900mV with appropriate tolerances.
6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
7. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
8. Typical values are at V
DD
= 2.5V, V
DDQ
= 1.8V, +25°C ambient.
9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.)
10.This value is the worst case mnimumV
IH
over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is V
IH
= 0.65 *V
DD
where V
DD
is 1.8V ± 0.15V.
However, the LVTTL translator is supplied by a 2.5V nomnal supply on this part. To ensure compliance with the specification, the translator was designed to accept the calculated
worst case value ( V
IH
= 0.65 *[1.8 - 0.15V]) rather than reference against a nomnal 1.8V supply.
11.This value is the worst case maximumV
IL
over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is V
IL
= 0.35 *V
DD
where V
DD
is 1.8V ± 0.15V.
However, the LVTTL translator is supplied by a 2.5V nomnal supply on this part. To ensure compliance with the specification, the translator was designed to accept the calculated
worst case value ( V
IL
= 0.35 *[1.8 + 0.15V]) rather than reference against a nomnal 1.8V supply.
Min.
Typ.
(8)
Max
Unit
V
I
= V
DDQ
/GND
V
I
= GND/V
DDQ
—
—
—
- 0.3
—
—
- 0.7
±5
±5
- 1.2
μ
A
V
V
V
DDQ
+ 0.3
1.073
(10)
—
—
V
V
0.683
(11)
0.2
825
—
975
—
V
900
mV
mV
mV
mV
V
REF
+ 100
—
—
V
REF
- 100
—
900
V
DDQ
- 0.4
V
DDQ
- 0.1
—
—
—
—
0.4
0.1
V
V
V
V
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