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參數(shù)資料
| 型號(hào)： | IDT5T9050PGGI8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | TSSOP-28 |
| 文件頁數(shù)： | 2/7頁 |
| 文件大?。?/td> | 52K |
| 代理商： | IDT5T9050PGGI8 |
INDUSTRIALTEMPERATURERANGE
2
IDT5T9050
2.5VSINGLEDATARATE1:5CLOCKBUFFERTERABUFFERJR.
TSSOP
TOP VIEW
PIN CONFIGURATION
GL
GN D
V DD
GN D
G
V DD
Q1
Q 2
Q5
GN D
Q 3
A
Q4
V DD
GN D
V DD
NC
19
15
16
17
18
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
Symbol
Description
Max
Unit
VDD
Power Supply Voltage
–0.5 to +3.6
V
VI
Input Voltage
–0.5 to +3.6
V
VO
Output Voltage
–0.5 to VDD +0.5
V
TSTG
Storage Temperature
–65 to +165
°C
TJ
Junction Temperature
150
°C
ABSOLUTE MAXIMUM RATINGS(1)
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Symbol
Parameter
Min
Typ.
Max.
Unit
CIN
Input Capacitance
—
6
—
pF
CAPACITANCE(1) (TA = +25°C, F = 1.0MHz)
NOTE:
1. This parameter is measured at characterization but not tested.
Symbol
Description
Min.
Typ.
Max.
Unit
TA
AmbientOperatingTemperature
–40
+25
+85
°C
VDD
InternalPowerSupplyVoltage
2.3
2.5
2.7
V
RECOMMENDED OPERATING RANGE
PIN DESCRIPTION
Symbol
I/O
Type
Description
A
I
LVTTL
Clockinput
G
I
LVTTL
Gate control for Qn outputs. When G is LOW, these outputs are enabled. When G is HIGH, these outputs are asynchronously
disabled to the level designated by GL(1).
GL
I
LVTTL
Specifies output disable level. If HIGH, the outputs disable HIGH. If LOW, the outputs disable LOW.
Qn
O
LVTTL
Clockoutputs
VDD
PWR
Power supply for the device core, inputs, and outputs
GND
PWR
Power supply return for power
NOTE:
1. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the possibility of runt
pulses or be able to tolerate them in down stream circuitry.
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