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參數(shù)資料
| 型號(hào)： | IDT5T929-29NLI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | PRECISION CLOCK GENERATOR OC-48 APPLICATIONS |
| 中文描述： | 精密時(shí)鐘發(fā)生器的OC - 48應(yīng)用 |
| 文件頁(yè)數(shù)： | 3/8頁(yè) |
| 文件大小： | 60K |
| 代理商： | IDT5T929-29NLI |
3
INDUSTRIAL TEMPERATURE RANGE
IDT5T929
PRECISION CLOCK GENERATOR OC-48 APPLICATIONS
LOCK
FREQUENCY DETECTOR
The
5T929
will lock to, and track, a valid CLKIN signal;
LOCK
will be low
when this has occurred. If CLKIN fails, the
5T929
PLL will smoothly switch
to lock to REFIN without generating any glitches on the output. The fact that
the PLL is locked to REFIN rather than CLKIN is indicated by a high state on
LOCK
. When a valid input is then applied to CLKIN, the
5T929
will smoothly
switch back to locking on CLKIN, and
LOCK
will go low.
LOCK
will also switch
to high should the frequency of CLKIN drift close to the limts of the VCO tuning
range.
OUTPUT FREQUENCY RANGE
SELmode
Q
OUT
/Q
OUT
L
155.5 - 166.6
H
622 - 666.5
Q
REG
/Q
REG
Unit
MHz
MHz
regenerated CLKIN/
CLKIN
regenerated CLKIN/
CLKIN
PIN DESCRIPTION
Pin Name
CLKIN,
CLKIN
I/O
I
Type
Description
Adjustable
(1)
Differential or single-ended clock input signal. For differential, LVPECL or LVDS supported. If left open-circuited, inputs will float
to LVTTL threshold voltage so that either input may be used as a single-ended input. A capacitor to ground should be connected
on the floating input.
Differential reference clock input. The reference clock input is used as an input to the PLL when CLKIN/
CLKIN
fails. Differential
or single-ended clock input signal. For differential, LVPECL or LVDS supported. If left open-circuited, inputs will float to LVTTL
threshold voltage so that either input may be used as a single-ended input. A capacitor to ground should be connected on the
floating input.
2 level input to select output frequency range for Q
OUT
/Q
OUT
and Q
REG
/Q
REG
(see Output Frequency Range table)
Power Down Control. Shuts off entire chip when LOW.
Differential clock output. LVPECL or LVDS outputs.
Regenerated clock output fromCLKIN/
CLKIN
, LVPECL, or LVDS outputs.
LOW when PLL is locked to CLKIN, HIGH in all other conditions
Factory testing only. This pin should be left unconnected.
No connection
Power Supply
Ground
REFIN,
REFIN
I
Adjustable
(1)
SELmode
PD
Q
OUT
, Q
OUT
Q
REG
, Q
REG
LOCK
TEST
NC
V
DD
GND
I
I
0
0
0
2-level
(2)
LVTTL
Adjustable
(3)
Adjustable
(3)
LVTTL
PWR
PWR
NOTES:
1. Inputs are capable of translating the following interface standards:
Single-ended 3.3V LVTTL levels
Single-ended 2.5V LVTTL levels
Differential LVPECL levels
Differential LVDS levels
2. 2-level inputs are static inputs and must be tied to V
DD
or GND.
3. Outputs can be LVPECL or LVDS.
INPUT FREQUENCY RANGE
(1)
19.4MHz - 20.9MHz
38.8MHz - 41.7MHz
77.7MHz - 83.4MHz
155.5MHz - 167MHz
311MHz - 334MHz
622MHz - 667MHz
NOTE:
1. The PLL will automatically detect the input frequency and adjust the multiply ratio to
generate the appropriate output frequency.
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