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參數資料
| 型號： | IDT5T940-30NLI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PRECISION CLOCK GENERATOR OC-192 APPLICATIONS |
| 中文描述： | 5T SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28 |
| 封裝： | PLASTIC, VFQFPN-28 |
| 文件頁數： | 3/10頁 |
| 文件大?。?/td> | 68K |
| 代理商： | IDT5T940-30NLI |
3
INDUSTRIAL TEMPERATURE RANGE
IDT5T940
PRECISION CLOCK GENERATOR OC-192 APPLICATIONS
INPUT FREQUENCY RANGE
CLK/REF
[1:0]
HH
HM
HL
MH
MM
ML
LH
LM
LL
Input Frequency Range
19.4MHz - 20.9MHz
reserved
38.8MHz - 41.7MHz
77.7MHz - 83.4MHz
Automatic Detection
155.5MHz - 167MHz
311MHz - 334MHz
reserved
622MHz - 667MHz
PLL BANDWIDTH SELECTION
PLLBW
[1:0]
Min.
LL
65KHz
LH
250KHz
HL
1MHz
HH
4MHz
Max.
120KHz
500KHz
2MHz
8MHz
Mn. CLKIN/REFIN
19.44MHz
19.44MHz
38.88MHz
155.52MHz
OUTPUT FREQUENCY RANGE
SELmode
Q
OUT
/Q
OUT
L
155.5 - 166.6
M
622 - 666.5
H
622 - 666.5
Q
REG
/Q
REG
Unit
MHz
MHz
MHz
regenerated CLKIN/
CLKIN
155.5 - 166.6
regenerated CLKIN/
CLKIN
PIN DESCRIPTION
Pin Name
CLKIN,
CLKIN
I/O
I
Type
Description
Adjustable
(1)
Differential or single-ended clock input signal. For differential, LVPECL or LVDS supported. If left open-circuited, inputs will float
to LVTTL threshold voltage so that either input may be used as a single-ended input. A capacitor to ground should be connected
on the floating input.
Differential reference clock input. The reference clock input is used as an input to the PLL when CLKIN/
CLKIN
fails. Differential
or single-ended clock input signal. For differential, LVPECL or LVDS supported. If left open-circuited, inputs will float to LVTTL
threshold voltage so that either input may be used as a single-ended input. A capacitor to ground should be connected on the
floating input.
3 level inputs controlling PLL feedback divider ratio. Automatic detection is used if both inputs are MID.
3 level input to select output frequency range for Q
OUT
/Q
OUT
and Q
REG
/Q
REG
(see Output Frequency Range table)
PLL Bandwidth Select Inputs (see PLL Bandwidth Selection table)
Power Down Control. Shuts off entire chip when LOW.
Differential clock output. LVPECL or LVDS outputs.
Regenerated clock output fromCLKIN/
CLKIN
, LVPECL, or LVDS outputs.
LOW when PLL is locked to CLKIN, HIGH in all other conditions
Power Supply
Ground
REFIN,
REFIN
I
Adjustable
(1)
CLK/REF
[1:0]
SELmode
PLLBW
[1:0]
PD
Q
OUT
, Q
OUT
Q
REG
, Q
REG
LOCK
V
DD
GND
I
I
I
I
0
0
0
3-level
(2)
3-level
(2)
LVTTL
LVTTL
Adjustable
(3)
Adjustable
(3)
LVTTL
PWR
PWR
NOTES:
1. Inputs are capable of translating the following interface standards:
Single-ended 3.3V LVTTL levels
Single-ended 2.5V LVTTL levels
Differential LVPECL levels
Differential LVDS levels
2. 3-level inputs are static inputs and must be tied to V
DD
or GND or left floating.
3. Outputs can be LVPECL or LVDS.
LOCK
FREQUENCY DETECTOR
The 5T940 will lock to, and track, a valid CLKIN signal;
LOCK
will be low
when this has occurred. If CLKIN fails, the 5T940 PLL will smoothly switch
to lock to REFIN without generating any glitches on the output. The fact that
the PLL is locked to REFIN rather than CLKIN is indicated by a high state on
LOCK
. When a valid input is then applied to CLKIN, the 5T940 will smoothly
switch back to locking on CLKIN, and
LOCK
will go low.
LOCK
will also switch
to high should the frequency of CLKIN drift close to the limts of the VCO tuning
range.
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