參數(shù)資料
型號: IDT723623
廠商: 濟南固锝電子器件有限公司
英文描述: High-Slew-Rate, Single-Supply Operational Amplifier 8-PDIP -40 to 105
中文描述: 的CMOS總線匹配SyncFIFOTM 256 × 36,512 × 36,1024 × 36
文件頁數(shù): 3/28頁
文件大?。?/td> 286K
代理商: IDT723623
3
COMMERCIAL TEMPERATURE RANGE
IDT723623/723633/723643 BUS-MATCHING SyncFIFO
256 x 36, 512 x 36, 1,024 x 36
is useful since it permts flushing of the FIFO memory without changing any
configuration settings.
These devices have two modes of operation: In the
IDT Standard mode
,
the first word written to an empty FIFO is deposited into the memory array. A
read operation is required to access that word (along with all other words
residing in memory). In the
First Word Fall Through mode
(FWFT), the first word
written to an empty FIFO appears automatically on the outputs, no read
operation required (Nevertheless, accessing subsequent words does neces-
sitate a formal read request). The state of the BE/
FWFT
pin during Reset
determnes the mode in use.
The FIFO has a combined Empty/Output Ready Flag (
EF
/OR ) and a
combined Full/Input Ready Flag (
FF
/IR). The
EF
and
FF
functions are selected
in the IDT Standard mode.
EF
indicates whether or not the FIFO memory is
empty.
FF
shows whether the memory is full or not. The IR and OR functions
are selected in the First Word Fall Through mode. IR indicates whether or not
the FIFO has available memory locations. OR shows whether the FIFO has data
available for reading or not. It marks the presence of valid data on the outputs.
The FIFO has a programmable Almost-Empty flag (
AE
) and a program-
mable Almost-Full flag (
AF
).
AE
indicates when a selected number of words
remain in the FIFO memory achieve a predetermned "almost-empty state".
AF
indicates when the FIFO contains more than a selected number of words.
FF
/IR and
AF
are two-stage synchronized to the port clock that writes data
into its array.
EF
/OR and
AE
are two-stage synchronized to the port clock that
reads data fromits array. Programmable offsets for
AE
and
AF
are loaded in
parallel using Port A or in serial via the SD input. The Serial Programmng Mode
pin (
SPM
) makes this selection. Three default offset settings are also provided.
The
AE
threshold can be set at 8, 16 or 64 locations fromthe empty boundary
and the
AF
threshold can be set at 8, 16 or 64 locations fromthe full boundary.
All these choices are made using the FS0 and FS1 inputs during Reset.
Two or more devices may be used in parallel to create wider data paths.
In First Word Fall Through mode, more than one device may be connected in
series to create greater word depths. The addition of external components is
unnecessary.
If, at any time, the FIFO is not actively performng a function, the chip will
automatically power down. During the power down state, supply current
consumption (I
CC
) is at a mnimum Initiating any operation (by activating control
inputs) will immediately take the device out of the Power Down state.
The IDT723623/723633/723643 are characterized for operation from0
°
C
to 70
°
C. Industrial temperature range (-40
°
C to +85
°
C) is available by special
order. They are fabricated using IDT’s high speed, submcron CMOS
technology.
相關(guān)PDF資料
PDF描述
IDT723623L12 CMOS BUS-MATCHING SyncFIFOTM 256 x 36, 512 x 36, 1,024 x 36
IDT723643 HIGH-SLEW-RATE, SINGLE-SUPPLY OPERATIONAL AMPLIFIERS 14-SOIC 0 to 70
IDT723643L12 HIGH-SLEW-RATE, SINGLE-SUPPLY OPERATIONAL AMPLIFIERS 14-PDIP 0 to 70
IDT723643L12PF HIGH-SLEW-RATE, SINGLE-SUPPLY OPERATIONAL AMPLIFIERS 14-PDIP 0 to 70
IDT72T51246L5BBI 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits
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