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參數(shù)資料
| 型號： | IDT723623 |
| 廠商： | 濟南固锝電子器件有限公司 |
| 英文描述： | High-Slew-Rate, Single-Supply Operational Amplifier 8-PDIP -40 to 105 |
| 中文描述： | 的CMOS總線匹配SyncFIFOTM 256 × 36，512 × 36，1024 × 36 |
| 文件頁數(shù)： | 4/28頁 |
| 文件大?。?/td> | 286K |
| 代理商： | IDT723623 |
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COMMERCIAL TEMPERATURE RANGE
IDT723623/723633/723643 BUS-MATCHING SyncFIFO
256 x 36, 512 x 36, 1,024 x 36
Symbol
A0-A35
AE
Name
I/O
I/O
O
Description
Port A Data
Almost-Empty
Flag (Port B)
Almost-Full
Flag (Port A)
Port B Data
Big-Endian/
First Word
Fall Through
36-bit bidirectional data port for side A.
Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words in the FIFO
is less than or equal to the value in the Almost-Empty B offset register, X.
Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty locations in the
FIFO is less than or equal to the value in the Almost-Full A offset register, Y.
36-bit bidirectional data port for side B.
This is a dual purpose pin. During Master Reset, a HIGH on BE will select Big-Endian operation. In this case,
depending on the bus size, the most significant byte or word written to Port A is read fromPort B first. A
LOW on BE will select Little-Endian operation. In this case, the least significant byte or word written to Port A
is read fromPort B first. After Master Reset, this pin selects the timng mode. A HIGH on
FWFT
selects IDT
Standard mode, a LOW selects First Word Fall Through mode. Once the timng mode has been selected, the
level on
FWFT
must be static throughout device operation.
A HIGH on this pin enables either byte or word bus width on Port B, depending on the state of SIZE. A
LOW selects long word operation. BMworks with SIZE and BE to select the bus size and endian
arrangement for Port B. The level of BMmust be static throughout device operation.
CLKA is a continuous clock that synchronizes all data transfers through Port A and can be asynchronous or
coincident to CLKB.
FF
/IR and
AF
are synchronized to the LOW-to-HIGH transition of CLKA.
CLKB is a continuous clock that synchronizes all data transfers through Port B and can be asynchronous or
coincident to CLKA.
EF
/OR and
AE
are synchronized to the LOW-to-HIGH transition of CLKB.
CSA
must be LOW to enable to LOW-to-HIGH transition of CLKA to read or write on Port A. The A0-A35
outputs are in the high-impedance state when
CSA
is HIGH.
CSB
must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write on Port B. The B0-B35
outputs are in the high-impedance state when
CSB
is HIGH.
This is a dual function pin. In the IDT Standard mode, the
EF
function is selected.
EF
indicates whether or
not the FIFO memory is empty. In the FWFT mode, the OR function is selected. OR indicates the presence of valid
data on the B0-B35 outputs, available for reading.
EF
/OR is synchronized to the LOW-to-HIGH transition of CLKB.
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on Port A.
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on Port B.
This is a dual function pin. In the IDT Standard mode, the
FF
function is selected.
FF
indicates whether or
not the FIFO memory is full. In the FWFT mode, the IR function is selected. IR indicates whether or not there
is space available for writing to the FIFO memory.
FF
/IR is synchronized to the LOW-to-HIGH transition of
CLKA.
FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register programmng. During Reset,
FS1/
SEN
and FS0/SD, together with
SPM
, select the flag offset programmng method. Three offset register
programmng methods are available: automatically load one of three preset values (8, 16, or 64), parallel
load fromPort A, and serial load.
AF
O
B0-B35
BE/
FWFT
I/O
I
BM
(1)
Bus-Match
Select (Port B)
I
CLKA
Port A Clock
I
CLKB
Port B Clock
I
CSA
Port A Chip
Select
Port B Chip
Select
Empty/Output
Ready Flag
(Port B)
Port A Enable
Port B Enable
Full/Input
Ready Flag
(Port A)
I
CSB
I
EF
/OR
O
ENA
ENB
FF
/IR
I
I
O
FS1/
SEN
Flag Offset
Select 1/
Serial Enable,
I
FS0/SD
Flag Offset
Select 0/
Serial Data
I
When serial load is selected for flag offset register programmng, FS1/
SEN
is used as an enable synchronous
to the LOW-to-HIGH transition of CLKA. When FS1/
SEN
is LOW, a rising edge on CLKA load the bit present
on FS0/SD into the X and Y registers. The number of bit writes required to programthe offset registers is 16
for the IDT723623, 18 for the IDT723633, and 20 for the IDT723643. The first bit write stores the Y-register
MSB and the last bit write stores the X-register LSB.
A HIGH level on MBA chooses a mailbox register for a Port A read or write operation.
MBA
Port A Mailbox
Select
Port B Mailbox
Select
I
MBB
I
A HIGH level on MBB chooses a mailbox register for a Port B read or write operation. When the B0-B35
outputs are active, a HIGH level on MBB selects data fromthe mail1 register for output and a LOW level
selects FIFO data for output.
MBF1
is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to
the mail1 register are inhibited while
MBF1
is LOW.
MBF1
is set HIGH by a LOW-to-HIGH transition of CLKB
when a Port B read is selected and MBB is HIGH.
MBF1
is set HIGH following either a Reset (
RS1
) or Partial
Reset (
PRS
).
MBF1
Mail1 Register
Flag
O
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDT723623L12PF | 功能描述:IC FIFO SYNC 1KX9 12NS 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723623L12PF8 | 功能描述:IC FIFO SYNC 1KX9 12NS 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723623L12PFG | 功能描述:IC FIFO 256X36 SYNC 12NS 128TQFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723623L12PFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 1KX9 12NS 128QFP |
| IDT723623L15PF | 功能描述:IC FIFO SYNC 1KX9 15NS 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應商設備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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