參數(shù)資料
型號: IDT723623
廠商: 濟(jì)南固锝電子器件有限公司
英文描述: High-Slew-Rate, Single-Supply Operational Amplifier 8-PDIP -40 to 105
中文描述: 的CMOS總線匹配SyncFIFOTM 256 × 36,512 × 36,1024 × 36
文件頁數(shù): 5/28頁
文件大?。?/td> 286K
代理商: IDT723623
5
COMMERCIAL TEMPERATURE RANGE
IDT723623/723633/723643 BUS-MATCHING SyncFIFO
256 x 36, 512 x 36, 1,024 x 36
Symbol
MBF2
Name
I/O
O
Description
Mail2 Register
Flag
MBF2
is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to the mail2
register are inhibited while
MBF2
is LOW.
MBF2
is set HIGH by a LOW-to-HIGH transition of CLKA when a Port
A read is selected and MBA is HIGH.
MBF2
is set HIGH following either a Reset (
RS2
) or Partial Reset (
PRS
).
A LOW on both pins initializes the FIFO read and write pointers to the first location of memory and sets the Port B
output register to all zeroes. A LOW-to-HIGH transition on
RS1
selects the programmng method (serial or parallel)
and one of three programmable flag default offsets. It also configures Port B for bus size and endian arrangement.
Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while
RS1
is LOW.
A LOW on this pin initializes the FIFO read and write pointers to the first location of memory and sets the Port B output
register to all zeroes. During Partial Reset, the currently selected bus size, endianarrangement, programmng
method (serial or parallel), and programmable flag settings are all retained.
A HIGH on this pin when BMis HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin when BMis
HIGH selects word (18-bit) bus size. SIZE works with BMand BE to select the bus size and endian arrangement
for Port B. The level of SIZE must be static throughout device operation.
A LOW on this pin selects serial programmng of partial flag offsets. A HIGH on this pin selects parallel
programmng or default offsets (8, 16, or 64).
A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to-HIGH transition
of CLKA. The A0-A35 outputs are in the HIGH impedance state when W/
R
A is HIGH.
A LOW selects a write operation and a HIGH selects a read operation on Port B for a LOW-to-HIGH transition
of CLKB. The B0-B35 outputs are in the HIGH impedance state when
W
/RB is LOW.
RS1
/
RS2
Resets
I
PRS
Partial Reset
I
SIZE
(1)
Bus Size Select
(Port B)
I
SPM
(1)
Serial Program-
mng Mode
Port A Write/
Read Select
Port B Write/
Read Select
I
W/
R
A
I
W
/RB
I
NOTE:
1. BM SIZE and
SPM
are not TTL compatible. These inputs should be tied to V
CC
or GND.
相關(guān)PDF資料
PDF描述
IDT723623L12 CMOS BUS-MATCHING SyncFIFOTM 256 x 36, 512 x 36, 1,024 x 36
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