參數(shù)資料
型號: IDT723623L12PF
廠商: 濟(jì)南固锝電子器件有限公司
英文描述: Automotive Catalog High-Slew-Rate Single-Supply Operational Amplifier 8-SOIC -40 to 125
中文描述: 的CMOS總線匹配SyncFIFOTM 256 × 36,512 × 36,1024 × 36
文件頁數(shù): 11/28頁
文件大小: 286K
代理商: IDT723623L12PF
11
COMMERCIAL TEMPERATURE RANGE
IDT723623/723633/723643 BUS-MATCHING SyncFIFO
256 x 36, 512 x 36, 1,024 x 36
/
SPM
H
H
H
H
L
L
L
L
FS1/
SEN
H
H
L
L
H
H
L
L
FSO/SD
H
L
H
L
L
H
H
L
RS1
X AND Y REGlSTERS
(1)
64
16
8
Parallel programmng via Port A
Serial Programmng via SD
reserved
reserved
reserved
NOTE:
1. X register holds the offset for
AE
; Y register holds the offset for
AF
.
— PARALLEL LOAD FROMPORT A
To programthe X and Y registers fromPort A, performa Reset on with
SPM
HIGH and FS0 and FS1 LOW during the LOW-to-HIGH transition of
RS1
.
After this reset is complete, the first two writes to the FIFO do not store data in
RAM. The first two write cycles load the offset registers in the order Y, X. On
the third write cycle the FIFO is ready to be loaded with a data word. See Figure
5,
Parallel Programmng of the Almost-Full Flag and Almost-Empty Flag
Offset Values after Reset (IDT Standard and FWFT modes),
for a detailed
timng diagram The Port A data inputs used by the offset registers are (A7-A0),
(A8-A0), or (A9-A0) for the IDT723623, IDT723633 or IDT723643, respec-
tively. The highest numbered input is used as the most significant bit of the binary
number in each case. Valid programmng values for the registers range from
1 to 252 for the IDT723623; 1 to 508 for the IDT723633; and 1 to 1,020 for the
IDT723643. After all the offset registers are programmed fromPort A the FIFO
begins normal operation.
— SERIAL LOAD
To programthe X and Y registers serially, initiate a Reset with
SPM
LOW,
FS0/SD LOW and FS1/
SEN
HIGH during the LOW-to-HIGH transition of
RS1
.
After this reset is complete, the X and Y register values are loaded bit-wise
through the FS0/SD input on each LOW-to-HIGH transition of CLKA that the
FS1/
SEN
input is LOW. There are 16-, 18- or 20-bit writes are needed to
complete the programmng for the IDT723623, IDT723633, or IDT723643,
respectively. The two registers are written in the order Y, X. Each register value
CSA
H
L
L
L
L
L
L
L
W/
R
A
X
H
H
H
L
L
L
L
ENA
X
L
H
H
L
H
L
H
MBA
X
X
L
H
L
L
H
H
CLKA
X
X
Data A (A0-A35) I/O
High-Impedance
Input
Input
Input
Output
Output
Output
Output
PORT FUNCTION
None
None
FIFO write
Mail1 write
None
None
None
Mail2 read (set
MBF2
HIGH)
X
X
/
./
CSB
H
L
L
L
L
L
L
L
W
/RB
X
L
L
L
H
H
H
H
ENB
X
L
H
H
L
H
L
H
MBB
X
X
L
H
L
L
H
H
CLKB
X
X
Data B (B0-B35) I/O
High-Impedance
Input
Input
Input
Output
Output
Output
Output
PORT FUNCTION
None
None
None
Mail2 write
None
FIFO read
None
Mail1 read (set
MBF1
HIGH)
X
X
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