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參數(shù)資料
| 型號： | IDT723623L12PF |
| 廠商： | 濟南固锝電子器件有限公司 |
| 英文描述： | Automotive Catalog High-Slew-Rate Single-Supply Operational Amplifier 8-SOIC -40 to 125 |
| 中文描述： | 的CMOS總線匹配SyncFIFOTM 256 × 36，512 × 36，1024 × 36 |
| 文件頁數(shù)： | 14/28頁 |
| 文件大?。?/td> | 286K |
| 代理商： | IDT723623L12PF |
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14
COMMERCIAL TEMPERATURE RANGE
IDT723623/723633/723643 BUS-MATCHING SyncFIFO
256 x 36, 512 x 36, 1,024 x 36
HIGH. For a 36-bit bus size, 36 bits of mailbox data are placed on B0-B35. For
an 18-bit bus size, 18 bits of mailbox data are placed on B0-B17. (In this case,
B18-B35 are indetermnate.) For a 9-bit bus size, 9 bits of mailbox data are
placed on B0-B8. (In this case, B9-B35 are indetermnate.)
The Mail2 Register Flag (
MBF2
) is set HIGH by a LOW-to-HIGH transition
on CLKA when a Port A read is selected by
CSA
, W/
R
A, and ENA with MBA
HIGH.
For a 36-bit bus size, 36 bits of mailbox data are placed on A0-A35. For
an 18-bit bus size, 18 bits of mailbox data are placed on A0-A17. (In this case,
A18-A35 are indetermnate.) For a 9-bit bus size, 9 bits of mailbox data are
placed on A0-A8. (In this case, A9-A35 are indetermnate.)
The data in a mail register remains intact after it is read and changes only
when new data is written to the register. The Endian Select feature has no effect
on mailbox data. For mail register and mail register flag timng diagrams, see
Figure 17 and 18.
BUS SIZING
The Port B bus can be configured in a 36-bit long word, 18-bit word, or
9-bit byte format for data read fromthe FIFO. The levels applied to the Port B
Bus Size Select (SIZE) and the Bus-Match Select (BM) determne the Port B
bus size. These levels should be static throughout FIFO operation. Both bus
size selections are implemented at the completion of Reset, by the time the Full/
Input Ready flag is set HIGH, as shown in Figure 2.
Two different methods for sequencing data transfer are available for Port
B when the bus size selection is either byte-or word-size. They are referred
to as Big-Endian (most significant byte first) and Little-Endian (least significant
byte first). The level applied to the Big-Endian Select (BE) input during the LOW-
to-HIGH transition of
RS1
selects the endian method that will be active during
FIFO operation. BE is a dont care input when the bus size selected for Port B
is long word. The endian method is implemented at the completion of Reset, by
the time the Full/Input Ready flag is set HIGH, as shown in Figure 2.
Only 36-bit long word data is written to or read fromthe FIFO memory
on the IDT723623/723633/723643. Bus-matching operations are done after
data is read fromthe FIFO RAM. These bus-matching operations are not
available when transferring data via mailbox registers. Furthermore, both the
word- and byte-size bus selections limt the width of the data bus that can be used
for mail register operations. In this case, only those byte lanes belonging to the
selected word- or byte-size bus can carry mailbox data. The remaining data
outputs will be indetermnate. The remaining data inputs will be dont care inputs.
For example, when a word-size bus is selected, then mailbox data can be
transmtted only between A0-A17 and B0-B17. When a byte-size bus is
selected, then mailbox data can be transmtted only between A0-A8 and B0-
B8. (See Figures 17 and 18).
BUS-MATCHING FIFO READS
Data is read fromthe FIFO RAMin 36-bit long word increments. If a long
word bus size is implemented, the entire long word immediately shifts to the FIFO
output register. If byte or word size is implemented on Port B, only the first one
or two bytes appear on the selected portion of the FIFO output register, with the
rest of the long word stored in auxiliary registers. In this case, subsequent FIFO
reads output the rest of the long word to the FIFO output register in the order
shown by Figure 2.
When reading data fromFIFO in byte or word format, the unused B0-B35
outputs are indetermnate.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT723623L15 | Quad, High Slew Rate, Single-Supply, Op Amp 14-SOIC 0 to 70 |
| IDT723623L15PF | Quad, High Slew Rate, Single-Supply, Op Amp 14-SOIC 0 to 70 |
| IDT723633 | Quad, High Slew Rate, Single-Supply, Op Amp 14-TSSOP 0 to 70 |
| IDT723633L12 | Quad, High Slew Rate, Single-Supply, Op Amp 14-TSSOP 0 to 70 |
| IDT723633L12PF | Quad, High Slew Rate, Single-Supply, Op Amp 14-TSSOP 0 to 70 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT723623L12PF8 | 功能描述:IC FIFO SYNC 1KX9 12NS 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723623L12PFG | 功能描述:IC FIFO 256X36 SYNC 12NS 128TQFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723623L12PFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 1KX9 12NS 128QFP |
| IDT723623L15PF | 功能描述:IC FIFO SYNC 1KX9 15NS 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723623L15PF8 | 功能描述:IC FIFO SYNC 1KX9 15NS 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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