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參數(shù)資料
| 型號： | IDT723623L15 |
| 廠商： | 濟南固锝電子器件有限公司 |
| 英文描述： | Quad, High Slew Rate, Single-Supply, Op Amp 14-SOIC 0 to 70 |
| 中文描述： | 的CMOS總線匹配SyncFIFOTM 256 × 36，512 × 36，1024 × 36 |
| 文件頁數(shù)： | 10/28頁 |
| 文件大小： | 286K |
| 代理商： | IDT723623L15 |
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10
COMMERCIAL TEMPERATURE RANGE
IDT723623/723633/723643 BUS-MATCHING SyncFIFO
256 x 36, 512 x 36, 1,024 x 36
A HIGH on the BE/
FWFT
input when the Reset (
RS1
) input goes from
LOW to HIGH will select a Big-Endian arrangement. In this case, the most
significant byte (word) of the long word written to Port A will be read fromPort
B first; the least significant byte (word) of the long word written to Port A will be
read fromPort B last.
A LOW on the BE/
FWFT
input when the Reset (
RS1
) input goes fromLOW
to HIGH will select a Little-Endian arrangement. In this case, the least significant
byte (word) of the long word written to Port A will be read fromPort B first; the
most significant byte (word) of the long word written to Port A will be read from
Port B last. Refer to Figure 2 for an illustration of the BE function. See Figure
3 (Reset) for an Endian select timng diagram
— TIMING MODE SELECTION
After Reset, the FWFT select function is active, permtting a choice between
two possible timng modes: IDT Standard mode or First Word Fall Through
(FWFT) mode. Once the Reset (
RS1
) input is HIGH, a HIGH on the BE/
FWFT
input during the next LOW-to-HIGH transition of CLKA and CLKB will select IDT
Standard mode. This mode uses the Empty Flag function (
EF
) to indicate
whether or not there are any words present in the FIFO memory. It uses the
Full Flag function (
FF
) to indicate whether or not the FIFO memory has any free
space for writing. In IDT Standard mode, every word read fromthe FIFO,
including the first, must be requested using a formal read operation.
Once the Reset (
RS1
) input is HIGH, a LOW on the BE/
FWFT
input during
the next LOW-to-HIGH transition of CLKA and CLKB will select FWFT mode.
This mode uses the Output Ready function (OR) to indicate whether or not there
is valid data at the data outputs (B0-B35). It also uses the Input Ready function
(IR) to indicate whether or not the FIFO memory has any free space for writing.
In the FWFT mode, the first word written to an empty FIFO goes directly to data
outputs, no read request necessary. Subsequent words must be accessed by
performng a formal read operation.
Following Reset, the level applied to the BE/
FWFT
input to choose the
desired timng mode must remain static throughout FIFO operation. Refer to
Figure 3 (Reset) for a First Word Fall Through select timng diagram
PROGRAMMING THE ALMOST-EMPTY AND ALMOST-FULL FLAGS
Two registers in the IDT723623/723633/723643 are used to hold the
offset values for the Almost-Empty and Almost-Full flags. The Almost-Empty flag
(
AE
) Offset register is labeled X and Almost-Full flag (
AF
) Offset register is labeled
Y. The offset registers can be loaded with preset values during the reset of the
FIFO, programmed in parallel using the FIFO’s Port A data inputs, or
programmed in serial using the Serial Data (SD) input (see Table 1).
SPM
, FS0/
SD and FS1/
SEN
function the same way in both IDT Standard and FWFT
modes.
— PRESET VALUES
To load a FIFO’s Almost-Empty flag and Almost-Full flag Offset registers
with one of the three preset values listed in Table 1, the Serial ProgramMode
(
SPM
) and at least one of the flag-select inputs must be HIGH during the LOW-
to-HIGH transition of the Reset input (
RS1
). For example, to load the preset
value of 64 into X and Y,
SPM
, FS0 and FS1 must be HIGH when
RS1
returns
HIGH. For the relevant preset value loading timng diagram see Figure 3.
RESET (
RS1
/
RS2
)
After power up, a Reset operation must be performed by providing a LOW
pulse to
RS1
and
RS2
simultaneously. Afterwards, the FIFO memory of the
IDT723623/723633/723643 undergoes a complete reset by taking its Reset
(
RS1
and
RS2
) input LOW for at least four Port A clock (CLKA) and four Port
B clock (CLKB) LOW-to-HIGH transitions. The Reset inputs can switch
asynchronously to the clocks. A Reset initializes the internal read and write
pointers and forces the Full/Input Ready flag (
FF
/IR) LOW, the Empty/Output
Ready flag (
EF
/OR) LOW, the Almost-Empty flag (
AE
) LOW, and the Almost-
Full flag (
AF
) HIGH. A Reset (
RS1
) also forces the Mailbox flag (
MBF1
) of the
parallel mailbox register HIGH, and at the same time the
RS2
and
MBF2
operate
likewise. After a Reset, the FIFO’s Full/Input Ready flag is set HIGH after two
write clock cycles to begin normal operation.
A LOW-to-HIGH transition on the FlFO Reset (
RS1
) input latches the value
of the Big-Endian (BE) input for determning the order by which bytes are
transferred through Port B.
A LOW-to-HIGH transition on the FlFO Reset (
RS1
) input also latches the
values of the Flag Select (FS0, FS1) and Serial Programmng Mode (
SPM
)
inputs for choosing the Almost-Full and Almost-Empty offset programmng
method (for details see Table 1,
Flag Programmng
, and Almost-Empty and
Almost-Full flag offset programmng section).The relevant Reset timng diagram
can be found in Figure 3.
PARTIAL RESET (
PRS
)
The FIFO memory of the IDT723623/723633/723643 undergoes a
limted reset by taking its associated Partial Reset (
PRS
) input LOW for at least
four Port A clock (CLKA) and four Port B clock (CLKB) LOW-to-HIGH transitions.
The Partial Reset input can switch asynchronously to the clocks. A Partial Reset
initializes the internal read and write pointers and forces the Full/Input Ready
flag (
FF
/IR) LOW, the Empty/Output Ready flag (
EF
/OR) LOW, the Almost-
Empty flag (
AE
) LOW, and the Almost-Full flag (
AF
) HIGH. A Partial Reset also
forces the Mailbox flag (
MBF1
,
MBF2
) of the parallel mailbox register HIGH.
After a Partial Reset, the FIFO’s Full/Input Ready flag is set HIGH after two clock
cycles to begin normal operation. See Figure 4,
Partial Reset (IDTStandard
and FWFT Modes)
for the relevant timng diagram
Whatever flag offsets, programmng method (parallel or serial), and timng
mode (FWFT or IDT Standard mode) are currently selected at the time a Partial
Reset is initiated, those settings will be remain unchanged upon completion of
the reset operation. A Partial Reset may be useful in the case where
reprogrammng a FIFO following a Reset would be inconvenient.
BIG-ENDIAN/FIRST WORD FALL THROUGH (BE/
FWFT
)
— ENDIAN SELECTION
This is a dual purpose pin. At the time of Reset, the BE select function is
active, permtting a choice of Big- or Little-Endian byte arrangement for data read
fromPort B. This selection determnes the order by which bytes (or words) of
data are transferred through this port. For the following illustrations, assume that
a byte (or word) bus size has been selected for Port B. (Note that when Port
B is configured for a long word size, the Big-Endian function has no application
and the BE input is a “dont care”
1
.)
NOTE:
1. Either a HIGH or LOW can be applied to a “dont care” input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily “dont care” (along with unused
inputs) must not be left open, rather they must be either HIGH or LOW.
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| IDT723623L15PF | 功能描述:IC FIFO SYNC 1KX9 15NS 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723623L15PF8 | 功能描述:IC FIFO SYNC 1KX9 15NS 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723624L12PF | 功能描述:IC FIFO SYNC 256X36X2 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723624L12PF8 | 功能描述:IC FIFO SYNC 256X36X2 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標準包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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