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參數(shù)資料
| 型號(hào)： | IDT723633L15PF |
| 廠商： | 濟(jì)南固锝電子器件有限公司 |
| 英文描述： | Quad, High Slew Rate, Single-Supply, Op Amp 14-SOIC -40 to 105 |
| 中文描述： | 的CMOS總線匹配SyncFIFOTM 256 × 36，512 × 36，1024 × 36 |
| 文件頁數(shù)： | 12/28頁 |
| 文件大?。?/td> | 286K |
| 代理商： | IDT723633L15PF |
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12
COMMERCIAL TEMPERATURE RANGE
IDT723623/723633/723643 BUS-MATCHING SyncFIFO
256 x 36, 512 x 36, 1,024 x 36
0/
Synchronized
to CLKB
EF
/OR
L
H
H
H
H
Synchronized
to CLKA
AF
H
H
H
L
L
Number of Words in FIFO
(1,2)
IDT723633
(3)
IDT723623
(3)
0
1 to X
(X+1) to [256-(Y+1)]
(256-Y) to 255
256
IDT723643
(3)
0
1 to X
(X+1) to [1,024-(Y+1)]
(1,024-Y) to 1,023
1,024
AE
L
L
H
H
H
FF
/IR
H
H
H
H
L
0
1 to X
(X+1) to [512-(Y+1)]
(512-Y) to 511
512
NOTES:
1.
2.
When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output
register (no read operation necessary), it is not included in the memory count.
X is the almost-empty offset used by
AE
. Y is the almost-full offset used by
AF
. Both X and Y are selected during a FIFO reset or Port A programmng.
3.
can be programmed from1 to 508 (IDT723623), 1 to 1,020 (IDT723633), or
1 to 2,044 (IDT723643).
When the option to programthe offset registers serially is chosen, the Full/
Input Ready (
FF
/IR) flag remains LOW until all register bits are written.
FF
/IR
is set HIGH by the LOW-to-HIGH transition of CLKA after the last bit is loaded
to allow normal FIFO operation.
See Figure 6,
Serial Programmng of the Almost-Full Flag and Almost-
Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes).
FIFO WRITE/READ OPERATION
The state of the Port A data (A0-A35) lines is controlled by Port A Chip Select
(
CSA
) and Port A Write/Read Select (W/
R
A). The A0-A35 lines are in the High-
impedance state when either
CSA
or W/
R
A is HIGH. The A0-A35 lines are active
outputs when both
CSA
and W/
R
A are LOW.
Data is loaded into the FIFO fromthe A0-A35 inputs on a LOW-to-HIGH
transition of CLKA when
CSA
is LOW, W/
R
A is HIGH, ENA is HIGH, MBA is
LOW, and
FF
/IR is HIGH (see Table 2). FIFO writes on Port A are independent
of any concurrent reads on Port B.
The Port B control signals are identical to those of Port A with the exception
that the Port B Write/Read select (
W
/RB) is the inverse of the Port A Write/Read
select (W/
R
A). The state of the Port B data (B0-B35) lines is controlled by the
Port B Chip Select (
CSB
) and Port B Write/Read select (
W
/RB). The B0-B35
lines are in the high-impedance state when either
CSB
is HIGH or
W
/RB is LOW.
The B0-B35 lines are active outputs when
CSB
is LOW and
W
/RB is HIGH.
Data is read fromthe FIFO to the B0-B35 outputs by a LOW-to-HIGH
transition of CLKB when
CSB
is LOW,
W
/RB is HIGH, ENB is HIGH, MBB is
LOW, and
EF
/OR is HIGH (see Table 3). FIFO reads on Port B are
independent of any concurrent writes on Port A.
The setup and hold time constraints to the port clocks for the port Chip
Selects and Write/Read selects are only for enabling write and read operations
and are not related to high-impedance control of the data outputs. If a port enable
is LOW during a clock cycle, the port’s Chip Select and Write/Read select may
change states during the setup and hold time window of the cycle.
When operating the FIFO in FWFT mode and the Output Ready flag is
LOW, the next word written is automatically sent to the FIFO’s output register
by the LOW-to-HIGH transition of the port clock that sets the Output Ready flag
HIGH. When the Output Ready flag is HIGH, data residing in the FIFOs memory
array is clocked to the output register only when a read is selected using the
port’s Chip Select, Write/Read select, Enable, and Mailbox select.
When operating the FIFO in IDT Standard mode, regardless of whether
the Empty Flag is LOW or HIGH, data residing in the FIFO’s memory array is
clocked to the output register only when a read is selected using the ports Chip
Select, Write/Read select, Enable, and Mailbox select. Port A Write timng
diagramcan be found in Figure 7. Relevant port B Read timng diagrams
together with Bus-Matching and Endian select can be found in Figure 8, 9 and
10.
SYNCHRONIZED FIFO FLAGS
Each FIFO is synchronized to its port clock through at least two flip-flop
stages. This is done to improve flag-signal reliability by reducing the probability
of metastable events when CLKA and CLKB operate asynchronously to one
another.
FF
/IR, and
AF
are synchronized to CLKA.
EF
/OR and
AE
are
synchronized to CLKB. Table 4 shows the relationship of each port flag to the
number of words stored in memory.
EMPTY/OUTPUT READY FLAGS (
EF
/OR)
These are dual purpose flags. In the FWFT mode, the Output Ready (OR)
function is selected. When the Output-Ready flag is HIGH, new data is present
in the FIFO output register. When the Output Ready flag is LOW, the previous
data word is present in the FIFO output register and attempted FIFO reads are
ignored.
In the IDT Standard mode, the Empty Flag (
EF
) function is selected. When
the Empty Flag is HIGH, data is available in the FIFO’s memory for reading to
the output register. When the Empty Flag is LOW, the previous data word is
present in the FIFO output register and attempted FIFO reads are ignored.
The Empty/Output Ready flag of a FIFO is synchronized to the port clock
that reads data fromits array (CLKB). For both the FWFT and IDT Standard
modes, the FIFO read pointer is incremented each time a new word is clocked
to its output register. The state machine that controls an Output Ready flag
monitors a write pointer and read pointer comparator that indicates when the
FIFO memory status is empty, empty+1, or empty+2.
In FWFT mode, fromthe time a word is written to a FIFO, it can be shifted
to the FIFO output register in a mnimumof three cycles of the Output Ready
flag synchronizing clock. Therefore, an Output Ready flag is LOW if a word in
memory is the next data to be sent to the FlFO output register and three cycles
of the port Clock that reads data fromthe FIFO have not elapsed since the time
the word was written. The Output Ready flag of the FIFO remains LOW until
the third LOW-to-HIGH transition of the synchronizing clock occurs, simulta-
neously forcing the Output Ready flag HIGH and shifting the word to the FIFO
output register.
In IDT Standard mode, fromthe time a word is written to a FIFO, the Empty
Flag will indicate the presence of data available for reading in a mnimumof two
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| IDT723623 | High-Slew-Rate, Single-Supply Operational Amplifier 8-PDIP -40 to 105 |
| IDT723623L12 | CMOS BUS-MATCHING SyncFIFOTM 256 x 36, 512 x 36, 1,024 x 36 |
| IDT723643 | HIGH-SLEW-RATE, SINGLE-SUPPLY OPERATIONAL AMPLIFIERS 14-SOIC 0 to 70 |
| IDT723643L12 | HIGH-SLEW-RATE, SINGLE-SUPPLY OPERATIONAL AMPLIFIERS 14-PDIP 0 to 70 |
| IDT723643L12PF | HIGH-SLEW-RATE, SINGLE-SUPPLY OPERATIONAL AMPLIFIERS 14-PDIP 0 to 70 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT723633L15PF8 | 功能描述:IC FIFO SYNC 512X36 128-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723634L12PF | 功能描述:IC FIFO SYNC 512X36X2 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723634L12PF8 | 功能描述:IC FIFO SYNC 512X36X2 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723634L15PF | 功能描述:IC FIFO SYNC 512X36X2 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723634L15PF8 | 功能描述:IC FIFO SYNC 512X36X2 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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