參數(shù)資料
型號(hào)： IDT72T51236L5BBI
廠商： Integrated Device Technology, Inc.
英文描述： 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits
中文描述： 2.5V的多隊(duì)列流量控制器件（4個(gè)隊(duì)列）36位寬度的配置589,824位，1179648和2359296位位
文件頁數(shù)： 10/62頁
文件大小： 622K
代理商： IDT72T51236L5BBI
10
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T51236/72T51246/72T51256 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
PIN DESCRIPTIONS (CONTINUED)
Symbol &
Name
Pin No.
PKT
(1)
(Continued)
Packet Mode
LVTTL
INPUT
connected. Packet Ready utilizes user marked locations to identify start and end of packets being written
into the device. Packet Mode can only be selected if both the input port width and output port width are
36 bits.
HSTL-LVTTL If packet mode has been selected this flag output provides Packet Ready status of the Queue selected
OUTPUT
for read operations. During a master reset the state of the PKT input determnes whether Packet mode
of operation will be used. If Packet mode is selected, then the condition of the
PR
flag and
OV
signal are
asserted indicates a packet is ready for reading. The user must mark the start of a packet and the end of
a packet when writing data into a queue. Using these Start Of Packet (SOP) and End Of Packet (EOP)
markers, the multi-queue device sets
PR
LOW if one or more “complete” packets are available in the queue.
A complete packet(s) must be written before the user is allowed to switch queues.
HSTL-LVTTL A Partial Reset can be performed on a single queue selected within the multi-queue device. Before a Partial
INPUT
Reset can be performed on a queue, that queue must be selected on both the write port and read port
2 clock cycles before the reset is performed. A Partial Reset is then performed by taking
PRS
LOW for
one WCLK cycle and one RCLK cycle. The Partial Reset will only reset the read and write pointers to
the first memory location, none of the devices configuration will be changed.
Data Output Bus HSTL-LVTTL These are the 36 data output pins. Data is read out of the device via these output pins on the rising edge
OUTPUT
of RCLK provided that
REN
is LOW,
OE
is LOW and the queue is selected. Note, that in Packet mode
Q32-Q35 may be used as packet markers, please see packet ready functional discussion for more
detail. Due to bus matching not all outputs may be used, any unused outputs should not be connected.
Read Address
HSTL-LVTTL The RADEN input is used in conjunction with RCLK and the RDADD address bus to select a queue to
Enable
INPUT
be read from A queue addressed via the RDADD bus is selected on the rising edge of RCLK provided
that RADEN is HIGH. RADEN should be asserted (HIGH) only during a queue change cycle(s). RADEN
should not be permanently tied HIGH. RADEN cannot be HIGH for the same RCLK cycle as ESTR. Note,
that a read queue selection cannot be made, (RADEN must NOT go active) until programmng of the
part has been completed and
SENO
has gone LOW.
Read Clock
HSTL-LVTTL When enabled by
REN
, the rising edge of RCLK reads data fromthe selected queue via the output
INPUT
bus Qout. The queue to be read is selected via the RDADD address bus and a rising edge of RCLK
while RADEN is HIGH. A rising edge of RCLK in conjunction with ESTR and RDADD will also select the
device to be placed on the
PAE
n/
PR
n bus during direct flag operation. During polled flag operation the
PAE
n/
PR
n bus is cycled with respect to RCLK and the ESYNC signal is synchronized to RCLK. The
PAE
,
PR
and
OV
outputs are all synchronized to RCLK. During device expansion the EXO and EXI signals
are based on RCLK. RCLK must be continuous and free-running.
Read Address
HSTL-LVTTL For the 4Q device the RDADD bus is 5 bits. The RDADD bus is a dual purpose address bus. The first
Bus
INPUT
function of RDADD is to select a queue to be read from The least significant 2 bits of the bus, RDADD[1:0]
are used to address 1 of 4 possible queues within a multi-queue device. The most significant 3 bits,
RDADD[4:2] are used to select 1 of 8 possible multi-queue devices that may be connected in expansion
mode. These 3 MSB’s will address a device with the matching ID code. The address present on the
RDADD bus will be selected on a rising edge of RCLK provided that RADEN is HIGH, (note, that data
can be placed on to the Qout bus, read fromthe previously selected queue on this RCLK edge). On the
next rising RCLK edge after a read queue select, a data word fromthe previous queue will be placed
onto the outputs, Qout, regardless of the
REN
input. Two RCLK rising edges after read queue select, data
will be placed on to the Qout outputs fromthe newly selected queue, regardless of
REN
due to the first
word fall through effect.
The second function of the RDADD bus is to select the device of queues to be loaded on to the
PAE
n/
PR
n bus during strobed flag mode. The most significant 3 bits, RDADD[4:2] are again used to select 1
of 8 possible multi-queue devices that may be connected in expansion mode. Address bits RDADD[1:0]
are dont care during device selection. The device address present on the RDADD bus will be selected
on the rising edge of RCLK provided that ESTR is HIGH, (note, that data can be placed on to the Qout
bus, read fromthe previously selected queue on this RCLK edge). Please refer to Table 2 for details on
RDADD bus.
PR
(R9)
Packet Ready
Flag
PRS
(T8)
Partial Reset
Q[35:0]
Qout
(See Pin No.
table for details)
RADEN
(R14)
RCLK
(T10)
RDADD
[4:0]
(RDADD4-P16
RDADD3-P15
RDADD2-P14
RDADD1-M16
RDADD0-M15)
I/O TYPE
Description
相關(guān)PDF資料
PDF描述
IDT72T51236L6BB 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits
IDT72T51236L6BBI 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits
IDT72T51246 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits
IDT72T51246L5BB 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits
IDT72T51246L6BB 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits
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