參數(shù)資料
型號(hào)： IDT72T51246L5BB
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： DRAM
英文描述： 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits
中文描述： 32K X 36 OTHER FIFO, 3.6 ns, PBGA256
封裝： 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256
文件頁(yè)數(shù)： 24/62頁(yè)
文件大小： 622K
代理商： IDT72T51246L5BB
24
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T51236/72T51246/72T51256 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
queues such that during a queue switch, the last data word required fromthe
previous queue will fall through the pipeline to the output.
Note, that if reads cease at the empty boundary of a queue, then the last word
will automatically flow through the pipeline to the output.
The Null Q operation is achieved by setting the Null Q signal HIGH during
a queue select. Note that the read address bus RDADD[6:0] is a don't care. The
Null Queue is a separate queue within the device and thus the maximumnumber
of queues and memory is always available regardless of whether or not the Null
queue is used. Also note that in expansion mode a user may want to use a
dedicated null queue for each device. A null queue can be selected when no
further reads are required froma previously selected queue. Changing to a null
queue will continue to propagate data in the pipeline to the previous queue's
output. The Null Q can remain selected until a data becomes available in another
queue for reading. The Null-Q can be utilized in either standard or packet mode.
Note: If the user switches the read port to the null queue, this queue is seen
as and treated as an empty queue, therefore after switching to the null queue
the last word fromthe previous queue will remain in the output register and the
OV
flag will go HIGH, indicating data is not valid.
The Null queue operation only has significance to the read port of the multi-
queue, it is a means to force data through the pipeline to the output. Null Q
selection and operation has no meaning on the write port of the device. Also,
refer to Figure 21,
Read Operation and Null Queue Select
for diagram
PAF
n FLAG BUS OPERATION
The IDT72T51236/72T51246/72T51256 multi-queue flow-control devices
can be configured for up to 4 queues, each queue having its own almost full
status. An active queue has its flag status output to the discrete flags,
FF
and
PAF
,
on the write port. Queues that are not selected for a write operation can have
their
PAF
status monitored via the
PAF
n bus. The
PAF
n flag bus is 4 bits wide,
so that all 4 queues can have their status output to the bus. When a single
multi-queue device is used anywhere from1 to 4 queues may be set-up within
the part, each queue having its own dedicated
PAF
flag output on the
PAF
n bus.
Queues 1 through 4 have their
PAF
status to
PAF
[0] through
PAF
[3]
respectively. If less than 4 queues are used then only the associated
PAF
n
outputs will be required, unused
PAF
n outputs will be dont care outputs. When
devices are connected in expansion mode the
PAF
n flag bus can also be
expanded beyond 4 bits to produce a wider
PAF
n bus that encompasses all
queues.
Alternatively, the 4 bit
PAF
n flag bus of each device can be connected together
to forma single 4 bit bus, i.e.
PAF
[0] of device 1 will connect to
PAF
[0] of device
2 etc. When connecting devices in this manner the
PAF
n can only be driven
by a single device at any time, (the
PAF
n outputs of all other devices must be
in high impedance state). There are two methods by which the user can select
which device has control of the bus, these are “Direct” (Addressed) mode or
“Polled” (Looped) mode, determned by the state of the FM(flag Mode) input
during a Master Reset.
EXPANDING UP TO 32 QUEUES OR PROVIDING DEEPER QUEUES
Expansion can take place using either the standard mode or the packet mode.
In the 4 queue multi-queue device, the WRADD address bus is 5 bits wide. The
2 Least Significant bits (LSbs) are used to address one of the 4 available queues
within a single multi-queue device. The 3 Most Significant bits (MSbs) are used
when a device is connected in expansion mode with up to 8 devices connected
in width expansion, each device having its own 3-bit address. When logically
expanded with multiple parts, each device is statically setup with a unique chip
ID code on the ID pins, ID0, ID1, and ID2. A device is selected when the 3 Most
Significant bits of the WRADD address bus matches a 3-bit ID code. The
maximumlogical expansion is 32 queues (4 queues x 8 devices) or a mnimum
of 8 queues (1 queue per device x 8 devices), each of the maximumsize of the
individual memory device.
Note: The WRADD bus is also used in conjunction with FSTR (almost full flag
bus strobe), to address the almost full flag bus during direct mode of operation.
Refer to Table 1, for Write Address bus arrangement. Also, refer to Figure
12,
Full Flag Timng Expansion Mode
, Figure 14,
Output Valid Flag Timng (In
Expansion Mode)
, and Figure 33,
Multi-Queue Expansion Diagram
, for timng
diagrams.
BUS MATCHING OPERATION
Bus Matching operation between the input port and output port is available.
During a master reset of the multi-queue the state of the three setup pins, BM
(Bus Matching), IW (Input Width) and OW (Output Width) determne the input and
output port bus widths as per the selections shown in Table 3, “Bus Matching
Set-Up”. 9 bit bytes, 18 bit words and 36 bit long words can be written into and
read formthe queues provided that at least one of the ports is setup for x36
operation. When writing to or reading fromthe multi-queue in a bus matching
mode, the device orders data in a “Little Endian” format. See Figure 4,
Bus
Matching Byte Arrangement
for details.
The Full flag and Almost Full flag operation is always based on writes and
reads of data widths determned by the write port width. For example, if the input
port is x36 and the output port is x9, then four data reads froma full queue will
be required to cause the full flag to go HIGH (queue not full). Conversely, the
Output Valid flag and Almost Empty flag operations are always based on writes
and reads of data widths determned by the read port. For example, if the input
port is x18 and the output port is x36, two write operations will be required to
cause the output valid flag of an empty queue to go LOW, output valid (queue
is not empty).
Note, that the input port serves all queues within a device, as does the output
port, therefore the input bus width to all queues is equal (determned by the input
port size) and the output bus width fromall queues is equal (determned by the
output port size).
BM
0
1
1
1
1
IW
X
0
0
1
1
OW
X
0
1
0
1
Write Port
x36
x36
x36
x18
x9
Read Port
x36
x18
x9
x36
x36
TABLE 3 — BUS-MATCHING SET-UP
FULL FLAG OPERATION
The multi-queue flow-control device provides a single Full Flag output,
FF
.
The
FF
flag output provides a full status of the queue currently selected on the
write port for write operations. Internally the multi-queue flow-control device
monitors and maintains a status of the full condition of all queues within it, however
only the queue that is selected for write operations has its full status output to the
FF
flag. This dedicated flag is often referred to as the “active queue full flag”.
When queue switches are being made on the write port, the
FF
flag output
will switch to the new queue and provide the user with the new queue status,
on the cycle after a new queue selection is made. The user then has a full status
for the new queue one cycle ahead of the WCLK rising edge that data can be
written into the new queue. That is, a new queue can be selected on the write
port via the WRADD bus, WADEN enable and a rising edge of WCLK. On the
second rising edge of WCLK, the
FF
flag output will show the full status of the
相關(guān)PDF資料
PDF描述
IDT72T51246L6BB 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits
IDT72T51246L6BBI 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits
IDT72T51256 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits
IDT72T51256L5BB 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits
IDT72T51256L5BBI 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits
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