參數(shù)資料
型號(hào)： IDT72T51246L5BB
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits
中文描述： 32K X 36 OTHER FIFO, 3.6 ns, PBGA256
封裝： 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256
文件頁數(shù)： 27/62頁
文件大?。?/td> 622K
代理商： IDT72T51246L5BB
27
IDT72T51236/72T51246/72T51256 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
TABLE 4 — FLAG OPERATION BOUNDARIES & TIMING
Output Valid,
OV
Flag Boundary
OV
Boundary Condition
In36 to out36 (Almost Empty Mode)
OV
Goes LOW after 1
st
Write
(Both ports selected for same queue
(see note 1 below for timng)
when the 1
st
Word is written in)
In36 to out36 (Packet Mode)
OV
Goes LOW after 1
st
Write
(Both ports selected for same queue
(see note 2 below for timng)
when the 1
st
Word is written in)
In36 to out18
OV
Goes LOW after 1
st
Write
(Both ports selected for same queue
(see note 1 below for timng)
when the 1
st
Word is written in)
In36 to out9
OV
Goes LOW after 1
st
Write
(Both ports selected for same queue
(see note 1 below for timng)
when the 1
st
Word is written in)
In18 to out36
OV
Goes LOW after 1
st
Write
(Both ports selected for same queue
(see note 1 below for timng)
when the 1
st
Word is written in)
In9 to out36
OV
Goes LOW after 1
st
Write
(Both ports selected for same queue
(see note 1 below for timng)
when the 1
st
Word is written in)
I/O Set-Up
NOTE:
1.
OV
Timing
Assertion:
Write to
OV
LOW: t
SKEW1
+ RCLK + t
ROV
If t
SKEW1
is violated there may be 1 added clock: t
SKEW1
+ 2 RCLK + t
ROV
De-assertion:
Read Operation to
OV
HIGH: t
ROV
2.
OV
Timing when in Packet Mode (36 in to 36 out only)
Assertion:
Write to
OV
LOW: t
SKEW4
+ RCLK + t
ROV
If t
SKEW4
is violated there may be 1 added clock: t
SKEW4
+ 2 RCLK + t
ROV
De-assertion:
Read Operation to
OV
HIGH: t
ROV
NOTE:
D = Queue Depth
FF
Timing
Assertion:
Write Operation to
FF
LOW: t
WFF
De-assertion:
Read to
FF
HIGH: t
SKEW1
+ t
WFF
If t
SKEW1
is violated there may be 1 added clock: t
SKEW1
+WCLK +t
WFF
Full Flag,
FF
Boundary
I/O Set-Up
FF
Boundary Condition
FF
Goes LOW after D+1 Writes
(see note below for timng)
In36 to out36
(Both ports selected for same queue
when the 1
st
Word is written in)
In36 to out36
(Write port only selected for queue
when the 1
st
Word is written in)
In36 to out18
(Both ports selected for same queue
when the 1
st
Word is written in)
In36 to out18
(Write port only selected for queue
when the 1
st
Word is written in)
In36 to out9
(Both ports selected for same queue
when the 1
st
Word is written in)
In36 to out9
(Write port only selected for queue
when the 1
st
Word is written in)
In18 to out36
(Both ports selected for same queue
when the 1
st
Word is written in)
In18 to out36
(Write port only selected for queue
when the 1
st
Word is written in)
In9 to out36
(Both ports selected for same queue
when the 1
st
Word is written in)
In9 to out36
(Write port only selected for queue
when the 1
st
Word is written in)
FF
Goes LOW after D Writes
(see note below for timng)
FF
Goes LOW after D Writes
(see note below for timng)
FF
Goes LOW after D Writes
(see note below for timng)
FF
Goes LOW after D Writes
(see note below for timng)
FF
Goes LOW after D Writes
(see note below for timng)
FF
Goes LOW after ([D+1] x 2) Writes
(see note below for timng)
FF
Goes LOW after (D x 2) Writes
(see note below for timng)
FF
Goes LOW after ([D+1] x 4) Writes
(see note below for timng)
FF
Goes LOW after (D x 4) Writes
(see note below for timng)
Programmable Almost Full Flag,
PAF
&
PAF
n Bus Boundary
I/O Set-Up
in36 to out36
(Both ports selected for same queue when the 1
st
Word is written in until the boundary is reached)
in36 to out36
(Write port only selected for same queue when the D-mWrites
1
st
Word is written in until the boundary is reached) (see note below for timng)
in36 to out18
PAF
&
PAF
n Boundary
PAF
/
PAF
n Goes LOW after
D+1-mWrites
(see note below for timng)
PAF
/
PAF
n Goes LOW after
PAF
/
PAF
n Goes LOW after
D-mWrites (see below for timng)
PAF
/
PAF
n Goes LOW after
D-mWrites (see below for timng)
PAF
/
PAF
n Goes LOW after
([D+1-m x 2) Writes
(see note below for timng)
PAF
/
PAF
n Goes LOW after
([D+1-m x 4) Writes
(see note below for timng)
in36 to out9
in18 to out36
in9 to out36
NOTE:
D = Queue Depth
m= Almost Full Offset value.
Default values:
if DF is LOW at Master Reset then m= 8
if DF is HIGH at Master Reset then m= 128
PAF
Timing
Assertion:
De-assertion: Read to
PAF
HIGH: t
SKEW2
+ WCLK + t
WAF
If t
SKEW2
is violated there may be 1 added clock: t
SKEW2
+ 2 WCLK + t
WAF
PAF
n Timing
Assertion:
Write Operation to
PAF
n LOW: 2 WCLK*+ t
PAF
De-assertion: Read to
PAF
n HIGH: t
SKEW3
+ WCLK*+ t
PAF
If t
SKEW3
is violated there may be 1 added clock: t
SKEW3
+ 2 WCLK* + t
PAF
*If a queue switch is occurring on the write port at the point of flag assertion or de-assertion
there may be one additional WCLK clock cycle delay.
Write Operation to
PAF
LOW: 2 WCLK + t
WAF
相關(guān)PDF資料
PDF描述
IDT72T51246L6BB 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits
IDT72T51246L6BBI 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits
IDT72T51256 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits
IDT72T51256L5BB 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits
IDT72T51256L5BBI 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits
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