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參數資料
| 型號： | IDT72T51246L6BBI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits |
| 中文描述： | 32K X 36 OTHER FIFO, 3.7 ns, PBGA256 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256 |
| 文件頁數： | 20/62頁 |
| 文件大?。?/td> | 622K |
| 代理商： | IDT72T51246L6BBI |
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20
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T51236/72T51246/72T51256 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
cycles are required for the device to load its internal setup registers. When a
single multi-queue device is used, the completion of device programmng is
signaled by the
SENO
output of a device going fromHIGH to LOW. Note, that
SENI
must be held LOW when a device is setup for default programmng mode.
When multi-queue devices are connected in expansion mode, the
SENI
of
the first device in a chain can be held LOW. The
SENO
of a device should
connect to the
SENI
of the next device in the chain. The
SENO
of the final device
is used to indicate that default programmng of all devices is complete. When the
final
SENO
goes LOW normal operations may begin. Again, all devices will be
programmed with their maximumnumber of queues and the memory divided
equally between them Please refer to Figure 9,
Default Programmng
.
READING AND WRITING TO THE IDT MULTI-QUEUE
FLOW-CONTROL DEVICE
The IDT72T51236/72T51246/72T51256 multi-queue flow-control devices
can be configured in two distinct modes, namely Standard Mode and Packet
Mode.
STANDARD MODE OPERATION (PKT = LOW ON MASTER RESET)
WRITE QUEUE SELECTION AND WRITE OPERATION
(STANDARD MODE)
The IDT72T51236/72T51246/72T51256 multi-queue flow-control devices
can be configured up to a maximumof 8 queues into which data can be written
via a common write port using the data inputs (Din), write clock (WCLK) and
write enable (
WEN
). The queue to be written is selected by the address present
on the write address bus (WRADD) during a rising edge on WCLK while write
address enable (WADEN) is HIGH. The state of
WEN
does not impact the queue
selection. The queue selection requires 1 WCLK cycle. All subsequent data
writes will be to this queue until another queue is selected.
Standard mode operation is defined as individual words will be written to the
device as opposed to Packet Mode where complete packets may be written.
The write port is designed such that 100% bus utilization can be obtained. This
means that data can be written into the device on every WCLK rising edge
including the cycle that a new queue is being addressed.
Changing queues requires a mnimumof 3 WCLK cycles on the write port
(see Figure 10,
Write Queue Select, Write Operation and Full flag Operation
).
WADEN goes high signaling a change of queue (clock cycle “A”). The address
on WRADD at that time determnes the next queue. Data presented during that
cycle (“A”) and the next cycle (“B” and “C”), will be written to the active (old)
queue, provided
WEN
is active LOW. If
WEN
is HIGH (inactive) for these 3 clock
cycles, data will not be written in to the previous queue. The write port discrete
full flag will update to show the full status of the newly selected queue (Q
) at this
last cycle’s rising edge (“C”). Data present on the data input bus (Din), can be
written into the newly selected queue (Q
) on the rising edge of WCLK on the
third cycle (“D”) following a change of queue, provided
WEN
is LOW and the
new queue is not full. If the newly selected queue is full at the point of its selection,
any writes to that queue will be prevented. Data cannot be written into a full
queue.
Refer to Figure 10,
Write Queue Select, Write Operation and Full flag
Operation
, Figure 11,
Write Operations & First Word Fall Through
for timng
diagrams and Figure 12,
Full Flag Timng in Expansion Mode
for timng
diagrams.
TABLE 1 — WRITE ADDRESS BUS, WRADD[4:0]
Operation WCLK WADEN
FSTR
WRADD[4:0]
Write Queue
Select
1
0
0
1
Device Select
(Compared to
ID0,1,2)
Write Queue Address
(2 bits = 4 Queues)
4
3
2
1 0
4
3
2
1
0
Device Select
(Compared to
ID0,1,2)
X
X
PAF
n Flag
Bus Device
Select
6116 drw05
相關PDF資料 |
PDF描述 |
|---|---|
| IDT72T51256 | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits |
| IDT72T51256L5BB | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits |
| IDT72T51256L5BBI | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits |
| IDT72T51256L6BB | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits |
| IDT72T51256L6BBI | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits |
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