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參數(shù)資料
| 型號： | IDT72T51246L6BBI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits |
| 中文描述： | 32K X 36 OTHER FIFO, 3.7 ns, PBGA256 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256 |
| 文件頁數(shù)： | 9/62頁 |
| 文件大?。?/td> | 622K |
| 代理商： | IDT72T51246L6BBI |
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IDT72T51236/72T51246/72T51256 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OE
(M14)
Output Enable
HSTL-LVTTL The Output enable signal is an Asynchronous signal used to provide three-state control of the multi-queue
INPUT
data output bus, Qout. If a device has been configured as a “Master” device, the Qout data outputs will
be in a Low Impedance condition if the
OE
input is LOW. If
OE
is HIGH then the Qout data outputs will be
in High Impedance. If a device is configured a “Slave” device, then the Qout data outputs will always be
in High Impedance until that device has been selected on the Read Port, at which point
OE
provides three-
state of that respective device.
HSTL-LVTTL This output flag provides output valid status for the data word present on the multi-queue flow-control device
OUTPUT
data output port, Qout. This flag is therefore, 2-stage delayed to match the data output path delay. That
is, there is a 2 RCLK cycle delay fromthe time a given queue is selected for reads, to the time the
OV
flag
represents the data in that respective queue. When a selected queue on the read port is read to empty,
the
OV
flag will go HIGH, indicating that data on the output bus is not valid. The
OV
flag also has High-
Impedance capability, required when multiple devices are used and the
OV
flags are tied together.
LVTTL
This pin is setup during Master Reset and must not toggle during any device operation. This pin is used
INPUT
in conjunction with IW and BMto setup the data input and output bus widths to be a combination of x9,
x18 or x36, (providing that one port is x36).
HSTL-LVTTL This pin provides the Almost-Empty flag status for the queue that has been selected on the output port
OUTPUT
for read operations, (selected via RCLK, RDADD and RADEN). This pin is LOW when the selected
queue is almost-empty. This flag output may be duplicated on one of the
PAE
n bus lines. This flag is
synchronized to RCLK.
HSTL-LVTTL On the 4Q device the
PAE
n/
PR
n bus is 8 bits wide. During a Master Reset this bus is setup for either
OUTPUT
Almost Empty mode or Packet mode. This output bus provides
PAE
/
PR
n status of 4 queues within a
selected device. During queue read/write operations these outputs provide programmable empty flag
status or packet ready status, in either direct or polled mode. The modeof flag operation is determned
during master reset via the state of the FMinput. This flag bus is capable of High-Impedance state, this
is important during expansion of multi-queue devices. During direct operation the
PAE
n/
PR
n bus is
updated to show the
PAE
/
PR
status of queues within a selected device. Selection is made using RCLK,
ESTR and RDADD. During Polled operation the
PAE
n/
PR
n bus is loaded with the
PAE
/
PR
n status of
multi-queue flow-control devices sequentially based on the rising edge of RCLK.
PAE
or
PR
operation
is determned by the state of PKT during master reset.
HSTL-LVTTL This pin provides the Almost-Full flag status for the queue that has been selected on the input port for
OUTPUT
write operations, (selected via WCLK, WRADD and WADEN). This pin is LOW when the selected queue
is almost-full. This flag output may be duplicated on one of the
PAF
n bus lines. This flag is synchronized
to WCLK.
HSTL-LVTTL On the 4Q device the
PAF
n bus is 8 bits wide. This output bus provides
PAF
status of 4 queues within
OUTPUT
a selected device. During queue read/write operations these outputs provide programmable full flag
status, in either direct or polled mode. The mode of flag operation is determned during master reset via
the state of the FMinput. This flag bus is capable of High-Impedance state, this is important during
expansion of multi-queue devices. During direct operation the
PAF
n bus is updated to show the
PAF
status
of queues within a selected device. Selection is made using WCLK, FSTR, WRADD and WADEN. During
Polled operation the
PAF
n bus is loaded with the
PAF
status of multi-queue flow-control devices sequentially
based on the rising edge of WCLK.
HSTL
This input is used to provide additional power savings. When the device I/O is setup for HSTL/eHSTL
INPUT
mode a HIGH on the PD input disables the data inputs on the write port only, providing significant power
savings. In LVTTL mode this pin has no operation
LVTTL
The state of this pin during a Master Reset will determne whether the part is operating in Packet mode
INPUT
providing both a Packet Ready (
PR
) output and a Programmable Almost Empty (PAE) discrete output,
or standard mode, providing a (
PAE
) output only. If this pin is HIGH during Master Reset the part will
operate in packet mode, if it is LOW then almost empty mode. If packet mode has been selected the
read port flag bus becomes packet ready flag bus,
PR
n and the discrete packet ready flag,
PR
is
functional. If almost empty operation has been selected then the flag bus provides almost empty status,
PAE
n and the discrete almost empty flag,
PAE
is functional, the
PR
flag is inactive and should not be
OV
(P9)
Output Valid
Flag
OW
(1)
(L16)
Output Width
PAE
(P10)
Programmable
Almost-Empty
Flag
PAE
n/
PR
n
(
PAE
3-P13
PAE
2-R13
PAE
1-T13
PAE
0-T14)
Programmable
Almost-Empty
Flag Bus/Packet
Ready Flag Bus
PAF
(R8)
Programmable
Almost-Full Flag
PAF
n
(
PAF
3-P5
PAF
2-R5
PAF
1-T5
PAF
0-T4)
Programmable
Almost-Full Flag
Bus
PD
(K1)
Power Down
PKT
(1)
(J14)
Packet Mode
PIN DESCRIPTIONS (CONTINUED)
Symbol &
Pin No.
Name
I/O TYPE
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72T51256 | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits |
| IDT72T51256L5BB | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits |
| IDT72T51256L5BBI | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits |
| IDT72T51256L6BB | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits |
| IDT72T51256L6BBI | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits |
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參數(shù)描述 |
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| IDT72T51248L5BB | 功能描述:IC FIFO 4KX8 5NS 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T51248L6-7BB | 功能描述:IC FIFO 4KX8 6-7NS 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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