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| 型號： | IDT72T51256L5BB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits |
| 中文描述： | 64K X 36 OTHER FIFO, 3.6 ns, PBGA256 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256 |
| 文件頁數(shù)： | 23/62頁 |
| 文件大?。?/td> | 622K |
| 代理商： | IDT72T51256L5BB |
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IDT72T51236/72T51246/72T51256 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
the queue, regardless of
REN
. For example, if a TSOP has been written and
some number of words later a TEOP is written a full packet of data is deemed
to be available, and the
PR
flag and
OV
will go active LOW. Consequently if reads
begin froma queue that has only one complete packet and the RSOP is detected
on the output port as data is being read out,
PR
will go inactive HIGH.
OV
will
remain LOW indicating there is still valid data being read out of that queue until
the REOP is read. The user may proceed with the reading operation until the
current packet has been read out and no further complete packets are available.
If during that time another complete packet has been written into the queue and
the
PR
flag will again gone active, then reads fromthe new packet may follow
after the current packet has been completely read out.
The packet counters therefore look for start of packet markers followed by end
of packet markers and regard data in between the TSOP and TEOP as a full
packet of data. The packet monitoring has no limtation as to how many packets
are written into a queue, the only constraint is the depth of the queue. Note, there
is a mnimumallowable packet size of four words, inclusive of the TSOP marker
and TEOP marker.
The packet logic does expect a TSOP marker to be followed by a TEOP
marker.
If a second TSOP marker is written after a first, it is ignored and the logic
regards data between the first TSOP and the first subsequent TEOP as the full
packet. The same is true for TEOP; a second consecutive TEOP mark is ignored.
On the read side the user should regard a packet as being between the first
RSOP and the first subsequent REOP and disregard consecutive RSOP
markers and/or REOP markers. This is why a TEOP may be written twice, using
the second TEOP as the “filler” word.
As an example, the user may also wish to implement the use of an “Almost
End of Packet” (AEOP) marker. For example, the AEOP can be assigned to
data input bit D33. The purpose of this AEOP marker is to provide an indicator
that the end of packet is a fixed (known) number of reads away fromthe end
of packet. This is a useful feature when due to latencies within the system
monitoring the REOP marker alone does not prevent “over reading” of the data
fromthe queue selected. For example, an AEOP marker set 4 writes before the
TEOP marker provides the device connected to the read port with and “almost
end of packet” indication 4 cycles before the end of packet.
The AEOP can be set any number of words before the end of packet
determned by user requirements or latencies involved in the system
See Figure 18,
Reading in Packet Mode during a Queue Change
, Figure
19,
Data Input (Transmt) Packet Mode of Operation
and Figure 20,
Data
Output (Receive) Packet Mode of Operation
.
PACKET MODE – MODULO OPERATION
The internal packet ready control logic performs no operation on these
modulo bits, they are only informational bits that are passed through with the
respective data byte(s).
When utilizing the
multi-queue flow-control device
in packet mode, the user
may also want to consider the implementation of “Modulo” operation or “valid
byte marking”. Modulo operation may be useful when the packets being
transferred through a queue are in a specific byte arrangement even though
the data bus width is 36 bits. In Modulo operation the user can concatenate bytes
to forma specific data string through the multi-queue device. A possible scenario
is where a limted number of bytes are extracted fromthe packet for either
analysis or filtered for security protection. This will only occur when the first 36
bit word of a packet is written in and the last 36 bit word of packet is written in.
The modulo operation is a means by which the user can mark and identify specific
data within the Queue.
On the write port data input bits, D32 (transmt modulo bit 2, TMOD2) and D33
(transmt modulo bit 1, TMOD1) can be used as data markers. An example of
this could be to use D32 and D33 to code which bytes of a word are part of the
packet that is also being marked as the “Start of Marker” or “End of Marker”.
Conversely on the read port when reading out these marked words, data
outputs Q32 (receive modulo bit 2, RMOD2) and Q33 (receive modulo bit 1,
RMOD1) will pass on the byte validity information for that word. Refer to Table
5 for one example of how the modulo bits may be setup and used. See Figure
19,
Data Input (Transmt) Packet Mode of Operation
and Figure 20,
Data
Output (Receive) Packet Mode of Operation
.
NULL QUEUE OPERATION (OF THE READ PORT)
Pipelining of data to the output port enables the device to provide 100% bus
utilization in standard mode. Data can be read out of the multi-queue flow-control
device on every RCLK cycle regardless of queue switches or other operations.
The device architecture is such that the pipeline is constantly filled with the next
words in a selected queue to be read out, again providing 100% bus utilization.
This type of architecture does assume that the user is constantly switching
BYTE A
BYTE B
BYTE C
BYTE D
D
D
TMOD1 (D33)
RMOD1 (Q33)
0
0
1
1
TMOD2 (D32)
RMOD2 (Q32)
0
1
0
1
VALID BYTES
A, B, C, D
A
A, B
A, B, C
D
D
D
D
D
D
M
M
S
E
D
6116 drw07
NOTE:
Packet Mode is only available when the Input Port and Output Port are 36 bits wide.
TABLE 5 — PACKET MODE VALID BYTE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72T51256L5BBI | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits |
| IDT72T51256L6BB | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits |
| IDT72T51256L6BBI | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits |
| IDT72T51543 | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION |
| IDT72T51543L5BB | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION |
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參數(shù)描述 |
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| IDT72T51258L5BB | 功能描述:IC FIFO 327768X20 5NS 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T51258L6-7BB | 功能描述:IC FIFO 327768X20 6-7NS 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T51258L6-7BBI | 功能描述:IC FIFO 327768X20 6-7NS 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T51268L5BB | 功能描述:IC FIFO 65536X20 5NS 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T51268L6-7BB | 功能描述:IC FIFO 65536X20 6-7NS 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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