- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379209 > IDT72T51256L6BB (INTEGRATED DEVICE TECHNOLOGY INC) 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits PDF資料下載
參數(shù)資料
| 型號： | IDT72T51256L6BB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits |
| 中文描述： | 64K X 36 OTHER FIFO, 3.7 ns, PBGA256 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256 |
| 文件頁數(shù)： | 2/62頁 |
| 文件大小： | 622K |
| 代理商： | IDT72T51256L6BB |
第1頁當前第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁
2
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T51236/72T51246/72T51256 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
DESCRIPTION:
The IDT72T51236/72T51246/72T51256 multi-queue flow-control de-
vices are single chip within which anywhere between 1 and 4 discrete FIFO
queues can be setup. All queues within the device have a common data input
bus, (write port) and a common data output bus, (read port). Data written into
the write port is directed to a respective queue via an internal de-multiplex
operation, addressed by the user. Data read fromthe read port is accessed
froma respective queue via an internal multiplex operation, addressed by the
user. Data writes and reads can be performed at high speeds up to 200MHz,
with access times of 3.6ns. Data write and read operations are totally
independent of each other, a queue maybe selected on the write port and a
different queue on the read port or both ports may select the same queue
simultaneously.
The device provides Full flag and Output Valid flag status for the queue
selected for write and read operations respectively. Also a Programmable
Almost Full and Programmable Almost Empty flag for each queue is provided.
Two 4 bit programmable flag busses are available, providing status of all
queues, including queues not selected for write or read operations, these flag
busses provide an individual flag per queue.
Bus Matching is available on this device, either port can be 9 bits, 18 bits
or 36 bits wide provided that at least one port is 36 bits wide. When Bus Matching
is used the device ensures the logical transfer of data throughput in a Little
Endian manner.
A packet mode of operation is also provided when the device is configured
for 36 bit input and 36 bit output port sizes. The Packet mode provides the user
with a flag output indicating when at least one (or more) packets of data within
a queue is available for reading. The Packet Ready provides the user with
a means by which to mark the start and end of packets of data being passed
through the queues. The multi-queue device then provides the user with
an internally generated packet ready status per queue.
The user has full flexibility configuring queues within the device, being able
to programthe total number of queues between 1 and 4, the individual queue
depths being independent of each other. The programmable flag positions are
also user programmable. All programmng is done via a dedicated serial port.
If the user does not wish to programthe multi-queue device, a default option is
available that configures the device in a predetermned manner.
Both Master Reset and Partial Reset pins are provided on this device. A Master
Reset latches in all configuration setup pins and must be performed before
programmng of the device can take place. A Partial Reset will reset the read and
write pointers of an individual queue, provided that the queue is selected on both
the write port and read port at the time of partial reset.
Echo Read Enable,
EREN
and Echo Read Clock, ERCLK outputs are
provided. These are outputs fromthe read port of the queue that are required
for high speed data communication, to provide tighter synchronization between
the data being transmtted fromthe Qn outputs and the data being received by
the input device. Data read fromthe read port is available on the output bus with
respect to
EREN
and ERCLK, this is very useful when data is being read at high
speed.
The multi-queue flow-control has the capability of operating its IO in either 2.5V
LVTTL, 1.5V HSTL or 1.8V eHSTL mode. The type of IO is selected via the
IOSEL input. The core supply voltage (V
CC
) to the multi-queue is always 2.5V,
however the output levels can be set independently via a separate supply, V
DDQ
.
The devices also provide additional power savings via a Power Down Input.
This input disables the write port data inputs when no write operations are
required.
A JTAG test port is provided, here the multi-queue flow-control device has a
fully functional Boundary Scan feature, compliant with IEEE 1149.1 Standard
Test Access Port and Boundary Scan Architecture.
See Figure 1,
Multi-Queue Flow-Control Device Block Diagram
for an outline
of the functional blocks within the device.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72T51256L6BBI | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits |
| IDT72T51543 | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION |
| IDT72T51543L5BB | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION |
| IDT72T51543L5BBI | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION |
| IDT72T51543L6BB | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72T51258L5BB | 功能描述:IC FIFO 327768X20 5NS 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T51258L6-7BB | 功能描述:IC FIFO 327768X20 6-7NS 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T51258L6-7BBI | 功能描述:IC FIFO 327768X20 6-7NS 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T51268L5BB | 功能描述:IC FIFO 65536X20 5NS 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T51268L6-7BB | 功能描述:IC FIFO 65536X20 6-7NS 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
發(fā)布緊急采購，3分鐘左右您將得到回復。