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參數(shù)資料
| 型號： | IDT72T51543 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION |
| 中文描述： | 2.5V的多隊(duì)列流量控制器件（32隊(duì)列）18位范圍配置 |
| 文件頁數(shù)： | 19/57頁 |
| 文件大?。?/td> | 564K |
| 代理商： | IDT72T51543 |
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IDT72T51543/72T51553 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
queue device is used, the completion of device programmng is signaled by the
SENO
output of a device going fromHIGH to LOW. Note, that
SENI
must be
held LOW when a device is setup for default programmng mode.
When multi-queue devices are connected in expansion mode, the
SENI
of
the first device in a chain can be held LOW. The
SENO
of a device should
connect to the
SENI
of the next device in the chain. The
SENO
of the final device
is used to indicate that default programmng of all devices is complete. When the
final
SENO
goes LOW normal operations may begin. Again, all devices will be
programmed with their maximumnumber of queues and the memory divided
equally between them Please refer to Figure 9,
Default Programmng
.
WRITE QUEUE SELECTION & WRITE OPERATION
The IDT72T51543/72T51553 multi-queue flow-control devices have up to
32 queues that data can be written into via a common write port using the data
inputs, Din, write clock, WCLK and write enable,
WEN
. The queue address
present on the write address bus, WRADD during a rising edge on WCLK while
write address enable, WADEN is HIGH, is the queue selected for write
operations. The state of
WEN
is dont care during the write queue selection
cycle. The queue selection only has to be made on a single WCLK cycle, this
will remain the selected queue until another queue is selected, the selected
queue is always the last queue selected.
The write port is designed such that 100% bus utilization can be obtained.
This means that data can be written into the device on every WCLK rising edge
including the cycle that a new queue is being addressed. When a new queue
is selected for write operations the address for that queue must be present on
the WRADD bus during a rising edge of WCLK provided that WADEN is HIGH.
A queue to be written to need only be selected on a single rising edge of WCLK.
All subsequent writes will be written to that queue until a new queue is selected.
A mnimumof 3 WCLK cycles must occur between queue selections on the write
port. On the next WCLK rising edge the write port discrete full flag will update
to show the full status of the newly selected queue. On the second rising edge
of WCLK, data present on the data input bus, Din can be written into the newly
selected queue provided that
WEN
is LOW and the new queue is not full. The
cycle of the queue selection and the next cycle will continue to write data present
on the data input bus, Din into the previous queue provided that
WEN
is active
LOW.
If
WEN
is HIGH, inactive for these 3 clock cycles, then data will not be written
in to the previous queue.
If the newly selected queue is full at the point of its selection, then writes to that
queue will be prevented, a full queue cannot be written into.
In the 32 queue multi-queue device the WRADD address bus is 8 bits wide.
The least significant 5 bits are used to address one of the 32 available queues
within a single multi-queue device. The most significant 3 bits are used when
a device is connected in expansion mode, up to 8 devices can be connected
in expansion, each device having its own 3 bit address. The selected device
is the one for which the address matches a 3 bit ID code, which is statically setup
on the ID pins, ID0, ID1, and ID2 of each individual device.
Note, the WRADD bus is also used in conjunction with FSTR (almost full flag
bus strobe), to address the almost full flag bus quadrant during direct mode of
operation.
Refer to Table 1, for Write Address bus arrangement. Also, refer to Figure
10,
Write Queue Select, Write Operation and Full flag Operation
and Figure
12,
Full Flag Timng Expansion Mode
for timng diagrams.
TABLE 1 — WRITE ADDRESS BUS, WRADD[7:0]
Operation WCLK WADEN
FSTR
WRADD[7:0]
Write
Queue
Select
1
0
0
1
Device Select
(Compared to
ID0,1,2)
Write Queue Address
(5 bits = 32 Queues)
7
6
5
4 3 2
1 0
7
6
5
4 3 2
1 0
Device Select
(Compared to
ID0,1,2)
X
X
X
Quadrant
Address
PAF
n
Quadrant
Select
Q0 : Q7
→
PAF
0 :
PAF
7
Q8 : Q15
→
PAF
0 :
PAF
7
Q16 : Q23
→
PAF
0 :
PAF
7
Q24 : Q31
→
PAF
0 :
PAF
7
Quadrant
Address
00
01
10
11
Queue Status on
PAF
n Bus
5999 drw05
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72T51543L5BB | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION |
| IDT72T51543L5BBI | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION |
| IDT72T51543L6BB | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION |
| IDT72T51543L6BBI | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION |
| IDT72T51553 | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION |
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