參數(shù)資料
型號(hào)： IDT72T51543L5BBI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION
中文描述： 64K X 18 OTHER FIFO, PBGA256
封裝： PLASTIC, BGA-256
文件頁(yè)數(shù)： 10/57頁(yè)
文件大?。?/td> 564K
代理商： IDT72T51543L5BBI
10
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T51543/72T51553 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
PIN DESCRIPTIONS (CONTINUED)
Symbol &
Name
Pin No.
RADEN
Read Address
(Continued)
Enable
RCLK
Read Clock
(T10)
I/O TYPE
Description
LVTTL
INPUT
LVTTL
INPUT
that a read queue selection cannot be made, (RADEN must NOT go active) until programmng of the part
has been completed and
SENO
has gone LOW.
When enabled by
REN
, the rising edge of RCLK reads data fromthe selected queue via the output
bus Qout. The queue to be read is selected via the RDADD address bus and a rising edge of RCLK
while RADEN is HIGH. A rising edge of RCLK in conjunction with ESTR and RDADD will also select the
PAE
n flag quadrant to be placed on the
PAE
n bus during direct flag operation. During polled flag operation
the
PAE
n bus is cycled with respect to RCLK and the ESYNC signal is synchronized to RCLK. The
PAE
and
OV
outputs are all synchronized to RCLK. During device expansion the EXO and EXI signals are
based on RCLK. RCLK must be continuous and free-running.
For the 32Q device the RDADD bus is 8 bits. The RDADD bus is a dual purpose address bus. The
first function of RDADD is to select a queue to be read from The least significant 5 bits of the bus,
RDADD[4:0] are used to address 1 of 32 possible queues within a multi-queue device. The most significant
3 bits, RDADD[7:5] are used to select 1 of 8 possible multi-queue devices that may be connected in
expansion mode. These 3 MSB’s will address a device with the matching ID code. The address present
on the RDADD bus will be selected on a rising edge of RCLK provided that RADEN is HIGH, (note, that
data can be placed on to the Qout bus, read fromthe previously selected queue on this RCLK edge).
On the next rising RCLK edge after a read queue select, a data word fromthe previous queue will be
placed onto the outputs, Qout, regardless of the
REN
input. Two RCLK rising edges after read queue
select, data will be placed on to the Qout outputs fromthe newly selected queue, regardless of
REN
due
to the first word fall through effect.
The second function of the RDADD bus is to select the quadrant of queues to be loaded on to the
PAE
n bus during strobed flag mode. The least significant 2 bits, RDADD[1:0] are used to select the
quadrant of a device to be placed on the
PAE
n bus. The most significant 3 bits, RDADD[7:5] are again
used to select 1 of 8 possible multi-queue devices that may be connected in expansion mode. Address
bits RDADD[4:2] are dont care during quadrant selection. The quadrant address present on the RDADD
bus will be selected on the rising edge of RCLK provided that ESTR is HIGH, (note, that data can be placed
on to the Qout bus, read fromthe previously selected queue on this RCLK edge). Please refer to Table 2
for details on RDADD bus.
The
REN
input enables read operations froma selected queue based on a rising edge of RCLK.
A queue to be read fromcan be selected via RCLK, RADEN and the RDADD address bus regardless
of the state of
REN
. Data froma newly selected queue will be available on the Qout output bus on the second
RCLK cycle after queue selection regardless of
REN
due to the FWFT operation. A read enable is not
required to cycle the
PAE
n bus (in polled mode) or to select the
PAE
n quadrant , (in direct mode).
If serial programmng of the multi-queue device has been selected during master reset, the SCLK input
clocks the serial data through the multi-queue device. Data setup on the SI input is loaded into the device
on the rising edge of SCLK provided that
SENI
is enabled, LOW. When expansion of devices is performed
the SCLK of all devices should be connected to the same source.
During serial programmng of a multi-queue device, data loaded onto the SI input will be clocked into the
part (via a rising edge of SCLK), provided the
SENI
input of that device is LOW. If multiple devices are
cascaded, the
SENI
input should be connected to the
SENO
output of the previous device. So when serial
loading of a given device is complete, its
SENO
output goes LOW, allowing the next device in the chain
to be programmed (
SENO
will follow
SENI
of a given device once that device is programmed). The
SENI
input of the master device (or single device), should be controlled by the user.
This output is used to indicate that serial programmng or default programmng of the multi-queue device
has been completed.
SENO
follows
SENI
once programmng of a device is complete. Therefore,
SENO
will go LOW after programmng provided
SENI
is LOW, once
SENI
is taken HIGH again,
SENO
will also
go HIGH. When the
SENO
output goes LOW, the device is ready to begin normal read/write operations.
If multiple devices are cascaded and serial programmng of the devices will be used, the
SENO
output
should be connected to the
SENI
input of the next device in the chain. When serial programmng of the
first device is complete,
SENO
will go LOW, thereby taking the
SENI
input of the next device LOW and
so on throughout the chain. When a given device in the chain is fully programmed the
SENO
output
RDADD
[7:0]
(RDADD7-P16
RDADD6-P15
RDADD5-P14
RDADD4-N16
RDADD3-N15
RDADD2-N14
RDADD1-M16
RDADD0-M15)
Read Address
Bus
LVTTL
INPUT
REN
(T11)
Read Enable
LVTTL
INPUT
SCLK
(N3)
Serial Clock
LVTTL
INPUT
SENI
(M2)
Serial Input
Enable
LVTTL
INPUT
SENO
(M1)
Serial Output
Enable
LVTTL
OUTPUT
相關(guān)PDF資料
PDF描述
IDT72T51543L6BB 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION
IDT72T51543L6BBI 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION
IDT72T51553 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION
IDT72T51553L5BB 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION
IDT72T51553L5BBI 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION
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