參數(shù)資料
型號(hào)： IDT72T51543L6BB
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： DRAM
英文描述： 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION
中文描述： 64K X 18 OTHER FIFO, 3.7 ns, PBGA256
封裝： 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256
文件頁(yè)數(shù)： 7/57頁(yè)
文件大?。?/td> 564K
代理商： IDT72T51543L6BB
7
IDT72T51543/72T51553 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTIONS
Symbol &
Pin No.
D[17:0]
Data Input Bus
Din (See Pin
table for details)
DF
(1)
Default Flag
(L3)
Name
I/O TYPE
Description
LVTTL
INPUT
These are the 18 data input pins. Data is written into the device via these input pins on the rising edge
of WCLK provided that
WEN
is LOW. Due to bus matching not all inputs may be used, any unused inputs
should be tied LOW.
If the user requires default programmng of the multi-queue device, this pin must be setup before Master
Reset and must not toggle during any device operation. The state of this input at master reset determnes
the value of the
PAE
/
PAF
flag offsets. If DF is LOW the value is 8, if DF is HIGH the value is 128.
The multi-queue device requires programmng after master reset. The user can do this serially via the
serial port, or the user can use the default method. If DFMis LOW at master reset then serial mode will
be selected, if HIGH then default mode is selected.
HSTL-LVTTL Read Clock Echo output, this output generates a clock based on the read clock input, this is used for
OUTPUT
Source Synchronous clocking where the receiving devices utilizes the ERCLK to clock data output from
the queue.
HSTL-LVTTL Read Enable Echo output, can be used in conjunction with the ERCLK output to load data output from
OUTPUT
the queue into the receiving device.
LVTTL
If direct operation of the
PAE
n bus has been selected, the ESTR input is used in conjunction with RCLK
INPUT
and the RDADD bus to select a quadrant of queues to be placed on to the
PAE
n bus outputs. A quadrant
addressed via the RDADD bus is selected on the rising edge of RCLK provided that ESTR is HIGH. If
Polled operations has been selected, ESTR should be tied inactive, LOW.
LVTTL
ESYNC is an output fromthe multi-queue device that provides a synchronizing pulse for the
PAE
n bus
OUTPUT
during Polled operation of the
PAE
n bus. During Polled operation each quadrant of queue status flags
is loaded on to the
PAE
n bus outputs sequentially based on RCLK. The first RCLK rising edge loads
quadrant 1 on to
PAE
n, the second RCLK rising edge loads quadrant 2 and so on. The fifth RCLK rising
edge will again load quadrant 1. During the RCLK cycle that quadrant 1 of a selected device is placed
on to the
PAE
n bus, the ESYNC output will be HIGH. For all other quadrants of that device, the ESYNC
output will be LOW.
LVTTL
The EXI input is used when multi-queue devices are connected in expansion mode and Polled
PAE
n
INPUT
bus operation has been selected . EXI of device ‘N connects directly to EXO of device ‘N-1’. The EXI
receives a token fromthe previous device in a chain. In single device mode the EXI input must be tied
LOW if the
PAE
n bus is operated in direct mode. If the
PAE
n bus is operated in polled mode the EXI input
must be connected to the EXO output of the same device. In expansion mode the EXI of the first device
should be tied LOW, when direct mode is selected.
LVTTL
EXO is an output that is used when multi-queue devices are connected in expansion mode and Polled
OUTPUT
PAE
n bus operation has been selected. EXO of device N connects directly to EXI of device N+1’. This
pin pulses when device N has placed its final (4th) quadrant on to the
PAE
n bus with respect to RCLK.
This pulse (token) is then passed on to the next device in the chain ‘N+1’ and on the next RCLK rising
edge the first quadrant of device N+1 will be loaded on to the
PAE
n bus. This continues through the chain
and EXO of the last device is then looped back to EXI of the first device. The ESYNC output of each device
in the chain provides synchronization to the user of this looping event.
LVTTL
This pin provides the full flag output for the active queue, that is, the queue selected on the input port
OUTPUT
for write operations, (selected via WCLK, WRADD bus and WADEN). On the WCLK cycle after a
queue selection, this flag will show the status of the newly selected queue. Data can be written to this queue
on the next cycle provided
FF
is HIGH. This flag has High-Impedance capability, this is important during
expansion of devices, when the
FF
flag output of up to 8 devices may be connected together on a common
line. The device with a queue selected takes control of the
FF
bus, all other devices place their
FF
output
into High-Impedance. When a queue selection is made on the write port this output will switch from
High-Impedance control on the next WCLK cycle. This flag is synchronized to WCLK.
LVTTL
This pin is setup before a master reset and must not toggle during any device operation. The state of the
INPUT
FMpin during Master Reset will determne whether the
PAF
n and
PAE
n flag busses operate in either
Polled or Direct mode. If this pin is HIGH the mode is Polled, if LOW then it will be Direct.
LVTTL
INPUT
DFM
(1)
(L2)
Default Mode
LVTTL
INPUT
ERCLK
(R10)
RCLK Echo
EREN
(R11)
ESTR
(R15)
REN
Echo
PAE
n Flag Bus
Strobe
ESYNC
(R16)
PAE
n Bus Sync
EXI
(T16)
PAE
n Bus
Expansion In
EXO
(T15)
PAE
n Bus
Expansion Out
FF
(P8)
Full Flag
FM
(1)
(K16)
Flag Mode
相關(guān)PDF資料
PDF描述
IDT72T51543L6BBI 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION
IDT72T51553 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION
IDT72T51553L5BB 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION
IDT72T51553L5BBI 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION
IDT72T51553L6BB 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION
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