參數(shù)資料
型號(hào)： IDT72T51543L6BBI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： DRAM
英文描述： 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION
中文描述： 64K X 18 OTHER FIFO, 3.7 ns, PBGA256
封裝： 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256
文件頁(yè)數(shù)： 8/57頁(yè)
文件大小： 564K
代理商： IDT72T51543L6BBI
8
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T51543/72T51553 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
PIN DESCRIPTIONS (CONTINUED)
Symbol &
Name
Pin No.
FSTR
PAF
n Flag Bus
(R4)
Strobe
I/O TYPE
Description
LVTTL
INPUT
If direct operation of the
PAF
n bus has been selected, the FSTR input is used in conjunction with WCLK
and the WRADD bus to select a quadrant of queues to be placed on to the
PAF
n bus outputs. A quadrant
addressed via the WRADD bus is selected on the rising edge of WCLK provided that FSTR is HIGH. If
Polled operations has been selected, FSTR should be tied inactive, LOW.
FSYNC is an output fromthe multi-queue device that provides a synchronizing pulse for the
PAF
n bus
during Polled operation of the
PAF
n bus. During Polled operation each quadrant of queue status flags
is loaded on to the
PAF
n bus outputs sequentially based on WCLK. The first WCLK rising edge loads
quadrant 1 on to
PAF
n, the second WCLK rising edge loads quadrant 2 and so on. The fifth WCLK rising
edge will again load quadrant 1. During the WCLK cycle that quadrant 1 of a selected device is placed
on to the
PAF
n bus, the FSYNC output will be HIGH. For all other quadrants of that device, the FSYNC
output will be LOW.
The FXI input is used when multi-queue devices are connected in expansion mode and Polled
PAF
n
bus operation has been selected. FXI of device ‘N connects directly to FXO of device ‘N-1’. The FXI
receives a token fromthe previous device in a chain. In single device mode the FXI input must be tied
LOW if the
PAF
n bus is operated in direct mode. If the
PAF
n bus is operated in polled mode the FXI input
must be connected to the FXO output of the same device. In expansion mode the FXI of the first device
should be tied LOW, when direct mode is selected.
FXO is an output that is used when multi-queue devices are connected in expansion mode and Polled
PAF
n bus operation has been selected . FXO of device N connects directly to FXI of device N+1’. This
pin pulses when device N has placed its final (4th) quadrant on to the
PAF
n bus with respect to WCLK.
This pulse (token) is then passed on to the next device in the chain N+1’ and on the next WCLK rising
edge the first quadrant of device N+1 will be loaded on to the
PAF
n bus. This continues through the chain
and FXO of the last device is then looped back to FXI of the first device. The FSYNC output of each device
in the chain provides synchronization to the user of this looping event.
For the 32Q multi-queue device the WRADD and RDADD address busses are 8 bits wide. When a queue
selection takes place the 3 MSbs of this 8 bit address bus are used to address the specific device (the
5 LSbs are used to address the queue within that device). During write/read operations the 3 MSbs
of the address are compared to the device ID pins. The first device in a chain of multi-queue’s (connected
in expansion mode), may be setup as ‘000’, the second as ‘001’ and so on through to device 8 which
is 111’, however the ID does not have to match the device order. In single device mode these pins should
be setup as 000’ and the 3 MSbs of the WRADD and RDADD address busses should be tied LOW. The
ID[2:0] inputs setup a respective devices ID during master reset. These ID pins must not toggle during
any device operation. Note, the device selected as the ‘Master does not have to have the ID of ‘000’.
This pin is used to select either HSTL or 2.5V LVTTL operation for the I/O. If HSTL or eHSTL I/O are
required then IOSEL should be tied LOW. If LVTTL I/O are required then it should be tied HIGH.
IW selects the bus width for the data input bus. If IW is LOW during a Master Reset then the bus width
is x18, if HIGH then it is x9.
The state of this input at Master Reset determnes whether a given device (within a chain of devices), is the
Master device or a Slave. If this pin is HIGH, the device is the master if it is LOW then it is a Slave. The master
device is the first to take control of all outputs after a master reset, all slave devices go to High-Impedance,
preventing bus contention. If a multi-queue device is being used in single device mode, this pin must
be set HIGH.
A master reset is performed by taking
MRS
fromHIGH to LOW, to HIGH. Device programmng is required
after master reset.
HSTL-LVTTL This pin is used on the read port when a Null-Q is required, it is used in conjunction with the RDADD
INPUT
address bus to address the Null-Q.
LVTTL
The Output enable signal is an Asynchronous signal used to provide three-state control of the multi-queue
INPUT
data output bus, Qout. If a device has been configured as a “Master” device, the Qout data outputs will
be in a Low Impedance condition if the
OE
input is LOW. If
OE
is HIGH then the Qout data outputs will be
in High Impedance. If a device is configured a “Slave” device, then the Qout data outputs will always be
FSYNC
(R3)
PAF
n Bus Sync
LVTTL
OUTPUT
FXI
(T2)
PAF
n Bus
Expansion In
LVTTL
INPUT
FXO
(T3)
PAF
n Bus
Expansion Out
LVTTL
OUTPUT
ID[2:0]
(1)
(ID2-C9
ID1-A10
ID0-B10)
Device ID Pins
LVTTL
INPUT
IOSEL
(C8)
IW
(1)
(L15)
MAST
(1)
(K15)
IO Select
LVTTL
INPUT
LVTTL
INPUT
LVTTL
INPUT
Input Width
Master Device
MRS
(T9)
NULL-Q
(J2)
OE
(M14)
Master Reset
LVTTL
INPUT
Null Queue
Select
Output Enable
相關(guān)PDF資料
PDF描述
IDT72T51553 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION
IDT72T51553L5BB 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION
IDT72T51553L5BBI 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION
IDT72T51553L6BB 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION
IDT72T51553L6BBI 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION
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