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參數(shù)資料
| 型號： | IDT72T51546 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| 中文描述： | 2.5V的多隊列流量控制器件（32隊列）36位寬度的配置1179648位和2359296位 |
| 文件頁數(shù)： | 21/64頁 |
| 文件大小： | 639K |
| 代理商： | IDT72T51546 |
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21
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
READ QUEUE SELECTION AND READ OPERATION
(STANDARD MODE)
The IDT72T51546/72T51556 multi-queue flow-control devices can be
configured up to a maximumof 32 queues which data can be read via a common
read port using the data outputs (Qout), read clock (RCLK) and read enable
(
REN
). An output enable,
OE
control pin is also provided to allow High-
Impedance selection of the Qout data outputs. The multi-queue device read port
operates in a mode simlar to “First Word Fall Through” on a SuperSync IDT
FIFO, but with the added feature of data output pipelining (see Figure 11,
Write
Operations & First Word Fall Through
). The queue to be read is selected by
the address presented on the read address bus (RDADD) during a rising edge
on RCLK while read address enable (RADEN) is HIGH. The state of
REN
does
not impact the queue selection. The queue selection requires 1 RCLK cycles.
All subsequent data reads will be fromthis queue until another queue is selected.
Standard mode operation is defined as individual words will be read fromthe
device as opposed to Packet Mode where complete packets may be read. The
read port is designed such that 100% bus utilization can be obtained. This means
that data can be read out of the device on every RCLK rising edge including
the cycle that a new queue is being addressed.
Changing queues requires a mnimumof three RCLK cycles on the read port
(see Figure 13,
Read Queue Select, Read Operation
). RADEN goes high
signaling a change of queue (clock cycle “D”). The address on RDADD at that
time determnes the next queue. Data presented during that cycle (“D”) will be
read at “D” (+ t
A
), and the next cycle (“E”), can continue to be read fromthe active
(old) queue (Q
), provided
REN
is active LOW. If
REN
is HIGH (inactive) for
these two clock cycles, data will not be read fromthe previous queue. The next
cycle’s rising edge (“F”), the read port discrete empty flag will update to show
the empty status of the newly selected queue (Q
). The internal pipeline is also
loaded at this time (“F”) with the last word fromthe previous (old) queue (Q
F
)
as well as the next word fromthe new queue (Q
F
). Both of these words will fall
through to the output register (provided the
OE
is asserted) consecutively
(cycles “F” and “G” respectively) following the selection of the new queue
regardless of the state of
REN
, unless the new queue (Q
) is empty. If the newly
selected queue is empty, any reads fromthat queue will be prevented. Data
cannot be read froman empty queue. The last word in the data output register
(fromthe previous queue), will remain on the data bus, but the output valid flag,
OV
will go HIGH, to indicate that the data present is no longer valid. This pipelining
effect provides the user with 100% bus utilization, and brings about the possibility
that a “NULL” queue may be required within a multi-queue device. Null queue
operation is discussed in the next section. Remember that
OE
allows the user
to place the data output bus (Qout) into High-Impedance and the data can be
read in to the output register regardless of
OE
.
Refer to Table 2, for Read Address Bus arrangement. Also, refer to Figures
13, 15, and 16 for read queue selection and read port operation timng diagrams.
PACKET MODE OPERATION (PKT = HIGH on Master Reset)
The Packet mode operation provides the capability where, user defined
packets or frames can be written to the device as opposed to Standard mode
where individual words are written. For clarification, in Packet Mode, a packet
can be written to the device with the starting location designated as Transmt Start
of Packet (TSOP) and the ending location designated as Transmt End of Packet
(TEOP). In conjunction, a packet read fromthe device will be designated as
Operation RCLK
RADEN
ESTR
RDADD[7:0]
Read Queue
Select
1
0
0
1
Device Select
(Compared to
ID0,1,2)
Read Queue Address
(5 bits = 32 Queues)
7
6
5
4 3 2
1 0
7
6
5
4 3 2
X
X
1 0
Quadrant
Address
Device Select
(Compared to
ID0,1,2)
X
PAE
n/
PR
n
Quadrant
Select
Q0 : Q7
→
PAE
0 :
PAE
7
Q8 : Q15
→
PAE
0 :
PAE
7
Q16 : Q23
→
PAE
0 :
PAE
7
Q24 : Q31
→
PAE
0 :
PAE
7
Quadrant
Address
00
01
10
11
Queue Status on
PAE
n/
PR
n Bus
5998 drw06
Null-Q
0
0
1
0
7
X
6
X
5
X
4 3 2
X
X
1 0
X
X
Null Queue
Select
1
X
TABLE 2 — READ ADDRESS BUS, RDADD[7:0]
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