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參數(shù)資料
| 型號： | IDT72T51546 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| 中文描述： | 2.5V的多隊列流量控制器件（32隊列）36位寬度的配置1179648位和2359296位 |
| 文件頁數(shù)： | 22/64頁 |
| 文件大小： | 639K |
| 代理商： | IDT72T51546 |
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22
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
Receive Start of Packet (RSOP) and a Receive End of Packet (REOP). The
mnimumsize for a packet is four words (SOP, two words of data and EOP). The
almost empty flag bus becomes the “Packet Ready”
PR
flag bus when the device
is configured for packet mode. Valid packets are indicated when both
PR
and
OV
are asserted.
WRITE QUEUE SELECTION AND WRITE OPERATION (PACKET MODE)
It is required that a full packet be written to a queue before moving to a different
queue. The device requires three cycles to change queues. Packet mode, has
2 restrictions: <1> An extra word (or filler word) is required to be written after
each packet on the cycle following the queue change to ensure the RSOP in
the old queue is not read out on a queue change because of the first word fall
through. <2> No SOP/EOP is allowed to read/written at cycle (“D” or “K”) the
second cycle after a queue change. In this mode, the write port may not obtain
100% bus utilization.
Changing queues requires a mnimumof 3 WCLK cycles on the write port
(see Figure 17,
Writing in Packet Mode during a Queue Change
). WADEN
goes high signaling a change of queue (clock cycle “B” or “I”). The address
on WRADD at the rising edge of WCLK determnes the next queue. Data
presented on Din during that cycle (“B” or “I”) and the next cycle (“C” or “J”)
can continue to be written to the active (old) queue (Q
or Q
respectively),
provided
WEN
is LOW (active). If
WEN
is HIGH (inactive) for these two clock
cycles (H), data will not be written in to the previous queue (Q
). The second
cycle following a request for queue change (“D” or “K”) will require a “filler” word
to be written to the device. This can be done by clocking the TEOP twice or by
writing a “filler” word. In packet mode, the multi-queue is designed under the
2 restrictions listed previously. Note, an erroneous Packet Ready flag may occur
if the EOP or SOP marker shows up at the second cycle after a queue change.
To prevent an erroneous Packet Ready flag fromoccurring a filler word should
be written into the old queue at the last clock cycle of writing. It is important to know
that no SOP or EOP may be written into the device during this cycle (“D” or “K”).
The write port discrete full flag will update to show the full status of the newly
selected queue (Q
) at this last cycle’s rising edge (“D” or “K”). Data values
presented on the data input bus (Din), can be written into the newly selected
queue (Q
) on the rising edge of WCLK on the third cycle (“E”) following a request
for change of queue, provided
WEN
is LOW (active) and the new queue is not
full. If a selected queue is full (
FF
is LOW), then writes to that queue will be
prevented. Note, data cannot be written into a full queue.
Refer to Figure 17,
Writing in Packet Mode during a Queue Change
and
Figure 19,
Data Input (Transit) Packet Mode of Operation
for timng diagrams.
READ QUEUE SELECTION AND READ OPERATION (PACKET MODE)
In packet Mode it is required that a full packet is read froma queue before
moving to a different queue. The device requires three cycles to change queues.
In Packet Mode, there are 2 restrictions <1> An extra word (or filler word) should
have been inserted into the data streamafter each packet to insure the RSOP
in the old queue is not read out on a queue change because of the first word
fall through and this word should be discarded. <2> No EOP/SOP is allowed
to be read/written at cycle (“D” or “K”) the second cycle after a queue change).
In this mode, the read port may not obtain 100% bus utilization.
Changing queues requires a mnimumof 3 RCLK cycles on the read port (see
Figure 18,
Reading in Packet Mode during a Queue Change
). RADEN goes
high signaling a change of queue (clock cycle “B” or “I”). The address on
RDADD at the rising edge of RCLK determnes the queue. As illustrated in Figure
18 during cycle (“B” or “I”), and the next cycle (“C” or “J”) data can continue
to be read fromthe active (old) queue (Q
or Q
respectively), provided both
REN
and
OE
are LOW (active) simultaneously with changing queues. REOP
for packet located in queue (Q
A
) must be read on or before a queue change
request is made (“C” or “J”). If
REN
is HIGH (inactive) for these two clock cycles,
data will not be read fromthe previous queue (Q
). In applications where the
multi-queue flow-control device is connected to a shared bus, an output enable,
OE
control pin is also provided to allow High-Impedance selection of the data
outputs (Qout). With reference to Figure 18 when changing queues, a packet
marker (SOP or EOP) should not be read on cycle (“E” or “L”). Reading a SOP
or EOP should not occur during the cycles required for a queue change. It is
also recommended that a queue change should not occur once the reading of
the packet has commenced, The EOP marker of the packet prior to a queue
change should be read on or before the queue change. If the EOP word is read
before a queue change,
REN
can be pulled high to disable further reads. When
the queue change is initiated, the filler word written into the current queue after
the EOP word will fall through followed by and the first word fromthe new queue.
Refer to Figure 18,
Reading in Packet Mode during a Queue Change
as
well as Figures 13, 15, and 16 for timng diagrams and Table 2, for Read Address
bus arrangement.
Note, the almost empty flag bus becomes the “Packet Ready” flag bus when
the device is configured for packet ready mode. .
PACKET READY FLAG
The 36-bit multi-queue flow-control device provides the user with a Packet
Ready feature. During a Master Reset the logic “1” (HIGH) on the PKT input
signal (packet mode select), configures the device in packet mode. The
PR
discrete flag, provides a packet ready status of the active queue selected on the
read port. A packet ready status is individually maintained on all queues;
however only the queue selected on the read port has its packet ready status
indicated on the
PR
output flag. A packet is available on the output for reading
when both
PR
and
OV
are asserted LOW. If less than a full packet is available,
the
PR
flag will be HIGH (packet not ready). In packet mode, no words can be
read froma queue until a complete packet has been written into that queue,
regardless of
REN
.
When packet mode is selected the Programmable Almost Empty bus,
PAE
n,
becomes the Packet Ready bus,
PR
n. When configured in Direct Bus (FM=
LOW during a master reset), the
PR
n bus provides packet ready status in 8
queue increments. The
PR
n bus supports either Polled or Direct modes of
operation. The
PR
n mode of operation is configured through the Flag Mode
(FM) bit during a Master Reset.
When the multi-queue is configured for packet mode operation, the device
must also be configured for 36 bit write data bus and 36 bit read data bus. The
two most significant bits of the 36-bit data bus are used as “packet markers”. On
the write port these are bits D34 (Transmt Start of Packet,) D35 (Transmt End
of Packet) and on the read port Q34, Q35. All four bits are monitored by the packet
control logic as data is written into and read out fromthe queues. The packet
ready status for individual queues is then determned by the packet ready logic.
On the write port D34 is used to “mark” the first word being written into the
selected queue as the “Transmt Start of Packet”, TSOP. To further clarify, when
the user requires a word being written to be marked as the start of a packet, the
TSOP input (D34) must be HIGH for the same WCLK rising edge as the word
that is written. The TSOP marker is stored in the queue along with the data it was
written in until the word is read out of the queue via the read port.
On the write port D35 is used to “mark” the last word of the packet currently
being written into the selected queue as the “Transmt End of Packet” TEOP.
When the user requires a word being written to be marked as the end of a packet,
the TEOP input must be HIGH for the same WCLK rising edge as the word that
is written in. The TEOP marker is stored in the queue along with the data it was
written in until the word is read out of the queue via the read port.
The packet ready logic monitors all start and end of packet markers both as
they enter respective queues via the write port and as they exit queues via the
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