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參數(shù)資料
| 型號(hào)： | IDT72T51546L5BB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| 中文描述： | 32K X 36 OTHER FIFO, 3.6 ns, PBGA256 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256 |
| 文件頁數(shù)： | 10/64頁 |
| 文件大?。?/td> | 639K |
| 代理商： | IDT72T51546L5BB |
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10
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
PIN DESCRIPTIONS (CONTINUED)
PKT
(1)
(Continued)
(J14)
PR
(R9)
Packet Mode
LVTTL
INPUT
the discrete almost empty flag,
PAE
is functional, the
PR
flag is inactive and should not be connected.
Packet Ready utilizes user marked locations to identify start and end of packets being written into the
device. Packet Mode can only be selected if both the input port width and output port width are 36 bits.
HSTL-LVTTL If packet mode has been selected this flag output provides Packet Ready status of the Queue selected
OUTPUT
for read operations. During a master reset the state of the PKT input determnes whether Packet mode
of operation will be used. If Packet mode is selected, then the condition of the
PR
flag and
OV
signal are
asserted indicates a packet is ready for reading. The user must mark the start of a packet and the end of
a packet when writing data into a queue. Using these Start Of Packet (SOP) and End Of Packet (EOP)
markers, the multi-queue device sets
PR
LOW if one or more “complete” packets are available in the queue.
A complete packet(s) must be written before the user is allowed to switch queues.
HSTL-LVTTL A Partial Reset can be performed on a single queue selected within the multi-queue device. Before a Partial
INPUT
Reset can be performed on a queue, that queue must be selected on both the write port and read port
2 clock cycles before the reset is performed. A Partial Reset is then performed by taking
PRS
LOW for
one WCLK cycle and one RCLK cycle. The Partial Reset will only reset the read and write pointers to
the first memory location, none of the devices configuration will be changed.
Data Output Bus HSTL-LVTTL These are the 36 data output pins. Data is read out of the device via these output pins on the rising edge
OUTPUT
of RCLK provided that
REN
is LOW,
OE
is LOW and the Queue is selected. Note, that in Packet Ready
mode Q32-Q35 may be used as packet markers, please see packet ready functional discussion for more
detail. Due to bus matching not all outputs may be used, any unused outputs should not be connected.
Read Address
HSTL-LVTTL The RADEN input is used in conjunction with RCLK and the RDADD address bus to select a queue to
Enable
INPUT
be read from A queue addressed via the RDADD bus is selected on the rising edge of RCLK provided
that RADEN is HIGH. RADEN should be asserted (HIGH) only during a queue change cycle(s). RADEN
should not be permanently tied HIGH. RADEN cannot be HIGH for the same RCLK cycle as ESTR. Note,
that a read queue selection cannot be made, (RADEN must NOT go active) until programmng of the
part has been completed and
SENO
has gone LOW.
Read Clock
HSTL-LVTTL When enabled by
REN
, the rising edge of RCLK reads data fromthe selected queue via the output
INPUT
bus Qout. The queue to be read is selected via the RDADD address bus and a rising edge of RCLK
while RADEN is HIGH. A rising edge of RCLK in conjunction with ESTR and RDADD will also select the
PAE
n/
PR
n flag quadrant to be placed on the
PAE
n/
PR
n bus during direct flag operation. During polled
flag operation the
PAE
n/
PR
n bus is cycled with respect to RCLK and the ESYNC signal is synchronized
to RCLK. The
PAE
,
PR
and
OV
outputs are all synchronized to RCLK. During device expansion the EXO
and EXI signals are based on RCLK. RCLK must be continuous and free-running.
Read Address
HSTL-LVTTL For the 32Q device the RDADD bus is 8 bits. The RDADD bus is a dual purpose address bus. The first
Bus
INPUT
function of RDADD is to select a Queue to be read from The least significant 5 bits of the bus, RDADD[4:0]
are used to address 1 of 32 possible queues within a multi-queue device. The most significant 3 bits,
RDADD[7:5] are used to select 1 of 8 possible multi-queue devices that may be connected in expansion
mode. These 3 MSB’s will address a device with the matching ID code. The address present on the
RDADD bus will be selected on a rising edge of RCLK provided that RADEN is HIGH, (note, that data
can be placed on to the Qout bus, read fromthe previously selected queue on this RCLK edge). On the
next rising RCLK edge after a read queue select, a data word fromthe previous queue will be placed
onto the outputs, Qout, regardless of the
REN
input. Two RCLK rising edges after read queue select,
data will be placed on to the Qout outputs fromthe newly selected queue, regardless of
REN
due to the
first word fall through effect.
The second function of the RDADD bus is to select the quadrant of queues to be loaded on to the
PAE
n/
PR
n bus during strobed flag mode. The least significant 2 bits, RDADD[1:0] are used to select the
quadrant of a device to be placed on the
PAE
n bus. The most significant 3 bits, RDADD[7:5] are again
used to select 1 of 8 possible multi-queue devices that may be connected in expansion mode. Address
bits RDADD[4:2] are dont care during quadrant selection. The quadrant address present on the RDADD
bus will be selected on the rising edge of RCLK provided that ESTR is HIGH, (note, that data can be placed
on to the Qout bus, read fromthe previously selected Queue on this RCLK edge). Please refer to Table 2
for details on RDADD bus.
Packet Ready
Flag
PRS
(T8)
Partial Reset
Q[35:0]
Qout
(See Pin No.
table for details)
RADEN
(R14)
RCLK
(T10)
RDADD
[7:0]
(RDADD7-P16
RDADD6-P15
RDADD5-P14
RDADD4-N16
RDADD3-N15
RDADD2-N14
RDADD1-M16
RDADD0-M15)
Symbol &
Pin No.
Name
I/O TYPE
Description
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