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| 型號： | IDT72T51546L5BB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| 中文描述： | 32K X 36 OTHER FIFO, 3.6 ns, PBGA256 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256 |
| 文件頁數(shù)： | 26/64頁 |
| 文件大?。?/td> | 639K |
| 代理商： | IDT72T51546L5BB |
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26
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
As mentioned, every queue within a multi-queue device has its own almost
full status, when a queue is selected on the write port, this status is output via the
PAF
flag. The
PAF
flag value for each queue is programmed during multi-queue
device programmng (along with the number of queues, queue depths and
almost empty values). The
PAF
offset value, m for a respective queue can be
programmed to be anywhere between 0’ and D’, where D’ is the total memory
depth for that queue. The
PAF
value of different queues within the same device
can be different values.
When queue switches are being made on the write port, the
PAF
flag output
will switch to the new queue and provide the user with the new queue status,
on the third cycle after a new queue selection is made, on the same WCLK cycle
that data can actually be written to the new queue. That is, a new queue can
be selected on the write port via the WRADD bus, WADEN enable and a rising
edge of WCLK. On the third rising edge of WCLK following a queue selection,
the
PAF
flag output will show the full status of the newly selected queue. The
PAF
is flag output is triple register buffered, so when a write operation occurs at the
almost full boundary causing the selected queue status to go almost full the
PAF
will go LOW 3 WCLK cycles after the write. The same is true when a read occurs,
there will be a 3 WCLK cycle delay after the read operation.
So the
PAF
flag delays are:
froma write operation to
PAF
flag LOW is 2 WCLK + t
WAF
The delay froma read operation to
PAF
flag HIGH is t
SKEW2
+ WCLK + t
WAF
Note, if t
SKEW
is violated there will be one added WCLK cycle delay.
The
PAF
flag is synchronous to the WCLK and all transitions of the
PAF
flag
occur based on a rising edge of WCLK. Internally the multi-queue device
monitors and keeps a record of the almost full status for all queues. It is possible
that the status of a
PAF
flag maybe changing internally even though that flag is
not the active queue flag (selected on the write port). A queue selected on the
read port may experience a change of its internal almost full flag status based
on read operations. The multi-queue flow-control device also provides a
duplicate of the
PAF
flag on the
PAF
[7:0] flag bus, this will be discussed in detail
in a later section of the data sheet.
See Figures 23 and 24 for Almost Full flag timng and queue switching.
ALMOST EMPTY FLAG
As previously mentioned the multi-queue flow-control device provides a
single Programmable Almost Empty flag output,
PAE
. The
PAE
flag output
provides a status of the almost empty condition for the active queue currently
selected on the read port for read operations. Internally the multi-queue flow-
control device monitors and maintains a status of the almost empty condition of
all queues within it, however only the queue that is selected for read operations
has its empty status output to the
PAE
flag. This dedicated flag is often referred
to as the “active queue almost empty flag”. The position of the
PAE
flag boundary
within a queue can be at any point within that queues depth. This location can
be user programmed via the serial port or one of the default values (8 or 128)
can be selected if the user has performed default programmng.
As mentioned, every queue within a multi-queue device has its own almost
empty status, when a queue is selected on the read port, this status is output via
the
PAE
flag. The
PAE
flag value for each queue is programmed during multi-
queue device programmng (along with the number of queues, queue depths
and almost full values). The
PAE
offset value, n, for a respective queue can be
programmed to be anywhere between 0’ and D’, where D’ is the total memory
depth for that queue. The
PAE
value of different queues within the same device
can be different values.
When queue switches are being made on the read port, the
PAE
flag output
will switch to the new queue and provide the user with the new queue status,
on the third cycle after a new queue selection is made, on the same RCLK cycle
that data actually falls through to the output register fromthe new queue. That
is, a new queue can be selected on the read port via the RDADD bus, RADEN
enable and a rising edge of RCLK. On the third rising edge of RCLK following
a queue selection, the data word fromthe new queue will be available at the
output register and the
PAE
flag output will show the empty status of the newly
selected queue. The
PAE
is flag output is triple register buffered, so when a read
operation occurs at the almost empty boundary causing the selected queue
status to go almost empty the
PAE
will go LOW 3 RCLK cycles after the read.
The same is true when a write occurs, there will be a 3 RCLK cycle delay after
the write operation.
So the
PAE
flag delays are:
froma read operation to
PAE
flag LOW is 2 RCLK + t
RAE
The delay froma write operation to
PAE
flag HIGH is t
SKEW2
+ RCLK + t
RAE
Note, if t
SKEW
is violated there will be one added RCLK cycle delay.
The
PAE
flag is synchronous to the RCLK and all transitions of the
PAE
flag
occur based on a rising edge of RCLK. Internally the multi-queue device
monitors and keeps a record of the almost empty status for all queues. It is possible
that the status of a
PAE
flag maybe changing internally even though that flag is
not the active queue flag (selected on the read port). A queue selected on the
write port may experience a change of its internal almost empty flag status based
on write operations. The multi-queue flow-control device also provides a
duplicate of the
PAE
flag on the
PAE
[7:0] flag bus, this will be discussed in detail
in a later section of the data sheet.
See Figures 25 and 26 for Almost Empty flag timng and queue switching.
POWER DOWN (PD)
This device has a power down feature intended for reducing power
consumption for HSTL/eHSTL configured inputs when the device is idle for a
long period of time. By entering the power down state certain inputs can be
disabled, thereby significantly reducing the power consumption of the part. All
WEN
and
REN
signals must be disabled for a mnimumof four WCLK and RCLK
cycles before activating the power down signal. The power down signal is
asynchronous and needs to be held LOW throughout the desired power down time.
During power down, the following conditions for the inputs/outputs signals are:
All data in Queue(s) memory are retained.
All data inputs become inactive.
All write and read pointers maintain their last value before power down.
All enables, chip selects, and clock input pins become inactive.
All data outputs become inactive and enter high-impedance state.
All flag outputs will maintain their current states before power down.
All programmable flag offsets maintain their values.
All echo clocks and enables will become inactive and enter high-
impedance state.
The serial programmng and JTAG port will become inactive and enter
high-impedance state.
All setup and configuration CMOS static inputs are not affected, as these
pins are tied to a known value and do not toggle during operation.
All internal counters, registers, and flags will remain unchanged and maintain
their current state prior to power down. Clock inputs can be continuous and free-
running during power down, but will have no affect on the part. However, it is
recommended that the clock inputs be low when the power down is active. To
exit power down state and resume normal operations, disable the power down
signal by bringing it HIGH. There must be a mnimumof 1
μ
s waiting period before
read and write operations can resume. The device will continue fromwhere it
had stopped and no formof reset is required after exiting power down state. The
power down feature does not provide any power savings when the inputs are
configured for LVTTL operation. However, it will reduce the current for I/Os that
are not tied directly to V
CC
or GND. See Figure 34,
Power Down Operation,
for the associated timng diagram
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