參數(shù)資料
型號： IDT72T51546L5BB
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
中文描述： 32K X 36 OTHER FIFO, 3.6 ns, PBGA256
封裝： 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256
文件頁數(shù)： 28/64頁
文件大?。?/td> 639K
代理商： IDT72T51546L5BB
28
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
TABLE 4 — FLAG OPERATION BOUNDARIES & TIMING (CONTINUED)
NOTE:
n = Almost Empty Offset value.
Default values: if DF is LOW at Master Reset then n = 8
if DF is HIGH at Master Reset then n = 128
PAE
n Timing
Assertion:
Read Operation to
PAE
n LOW: 2 RCLK*+ t
PAE
De-assertion: Write to
PAE
n HIGH: t
SKEW3
+ RCLK*+ t
PAE
If t
SKEW3
is violated there may be 1 added clock: t
SKEW3
+ 2 RCLK*+ t
PAE
*If a queue switch is occurring on the read port at the point of flag assertion or de-assertion
there may be one additional RCLK clock cycle delay.
Programmable Almost Empty Flag Bus,
PAE
n Boundary
I/O Set-Up
in36 to out36
(Both ports selected for same queue when the 1
st
Word is written in until the boundary is reached)
in36 to out36
(Write port only selected for same queue when the n+1 Writes
1
st
Word is written in until the boundary is reached) (see note below for timng)
in36 to out18
PAE
n Boundary Condition
PAE
n Goes HIGH after
n+2 Writes
(see note below for timng)
PAE
n Goes HIGH after
PAE
n Goes HIGH after n+1
Writes (see below for timng)
PAE
n Goes HIGH after n+1
Writes (see below for timng)
PAE
n Goes HIGH after
([n+2] x 2) Writes
(see note below for timng)
PAE
n Goes HIGH after
in36 to out9
in18 to out36
(Both ports selected for same queue when the 1
st
Word is written in until the boundary is reached)
in18 to out36
(Write port only selected for same queue when the ([n+1] x 2) Writes
1
st
Word is written in until the boundary is reached) (see note below for timng)
in9 to out36
(Both ports selected for same queue when the 1
st
Word is written in until the boundary is reached)
in9 to out36
(Write port only selected for same queue when the ([n+1] x 4) Writes
1
st
Word is written in until the boundary is reached) (see note below for timng)
PAE
n Goes HIGH after
([n+2] x 4) Writes
(see note below for timng)
PAE
n Goes HIGH after
NOTE:
n = Almost Empty Offset value.
Default values:
if DF is LOW at Master Reset then n = 8
if DF is HIGH at Master Reset then n = 128
PAE
Timing
Assertion:
De-assertion: Write to
PAE
HIGH: t
SKEW2
+ RCLK + t
RAE
If t
SKEW2
is violated there may be 1 added clock: t
SKEW2
+ 2 RCLK + t
RAE
Read Operation to
PAE
LOW: 2 RCLK + t
RAE
Programmable Almost Empty Flag,
PAE
Boundary
I/O Set-Up
in36 to out36
(Both ports selected for same queue when the 1
st
Word is written in until the boundary is reached)
in36 to out18
(Both ports selected for same queue when the 1
st
Word is written in until the boundary is reached)
in36 to out9
(Both ports selected for same queue when the 1
st
Word is written in until the boundary is reached)
in18 to out36
(Both ports selected for same queue when the 1
st
Word is written in until the boundary is reached)
in9 to out36
(Both ports selected for same queue when the 1
st
Word is written in until the boundary is reached)
PAE
Assertion
PAE
Goes HIGH after n+2
Writes
(see note below for timng)
PAE
Goes HIGH after n+1
Writes
(see note below for timng)
PAE
Goes HIGH after n+1
Writes
(see note below for timng)
PAE
Goes HIGH after
([n+2] x 2) Writes
(see note below for timng)
PAE
Goes HIGH after
([n+2] x 4) Writes
(see note below for timng)
PACKET READY FLAG,
PR
BOUNDARY
Assertion:
Both the rising and falling edges of
PR
are synchronous to RCLK.
PR
Falling Edge occurs upon writing the first TEOP marker, on input D35,
(assumng a TSOP marker, on input D34 has previously been written). i.e. a
complete packet is available within a queue.
Timing:
FromWCLK rising edge writing the TEOP word
PR
goes LOW after: t
SKEW4
+ 2 RCLK + t
PR
If t
SKEW4
is violated:
PR
goes LOW after t
SKEW4
+ 3 RCLK + t
PR
(Please refer to Figure 19,
Data Input (Transmt) Packet Mode of Operation,
for timng diagram.
De-assertion:
PR
Rising Edge occurs upon reading the last RSOP marker, fromoutput Q34.
i.e. there are no more complete packets available within the queue.
Timing:
FromRCLK rising edge Reading the RSOP word the
PR
goes HIGH after:
3 RCLK + t
PR
(Please refer to Figure 20,
Data Output (Receive) Packet Mode of Operation
for timng diagram.
PACKET READY FLAG BUS,
PR
n BOUNDARY
Assertion:
Both the rising and falling edges of
PR
n are synchronous to RCLK.
PR
n Falling Edge occurs upon writing the first TEOP marker, on input D35,
(assumng a TSOP marker, on input D34 has previously been written). i.e. a
complete packet is available within a queue.
Timing:
FromWCLK rising edge writing the TEOP word
PR
goes LOW after: t
SKEW4
+ 2 RCLK*+ t
PAE
If t
SKEW4
is violated
PR
n goes LOW after t
SKEW4
+ 3 RCLK*+ t
PAE
*f a queue switch is occurring on the read port at the point of flag assertion there
may be one additional RCLK clock cycle delay.
De-assertion:
PR
Rising Edge occurs upon reading the last RSOP marker, fromoutput Q34.
i.e. there are no more complete packets available within the queue.
Timing:
FromRCLK rising edge Reading the RSOP word the
PR
goes HIGH after:
3 RCLK*+ t
PAE
*If a queue switch is occurring on the read port at the point of flag assertion or
de-assertion there may be one additional RCLK clock cycle delay.
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