參數(shù)資料
型號(hào)： IDT72T51553
廠商： Integrated Device Technology, Inc.
英文描述： 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION
中文描述： 2.5V的多隊(duì)列流量控制器件（32隊(duì)列）18位范圍配置
文件頁(yè)數(shù)： 9/57頁(yè)
文件大小： 564K
代理商： IDT72T51553
9
IDT72T51543/72T51553 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTIONS (CONTINUED)
Symbol &
Pin No.
OE
(Continued)
OV
(P9)
Name
I/O TYPE
Description
Output Enable
LVTTL
OUTPUT
LVTTL
OUTPUT
in High Impedance until that device has been selected on the Read Port, at which point
OE
provides three-
state of that respective device.
This output flag provides output valid status for the data word present on the multi-queue flow-control
device data output port, Qout. This flag is therefore, 2-stage delayed to match the data output path delay.
That is, there is a 2 RCLK cycle delay fromthe time a given queue is selected for reads, to the time the
OV
flag represents the data in that respective queue. When a selected queue on the read port is read
to empty, the
OV
flag will go HIGH, indicating that data on the output bus is not valid. The
OV
flag also has
High-Impedance capability, required when multiple devices are used and the
OV
flags are tied together.
OW selects the bus width for the data output bus. If OW is LOW during a Master Reset then the bus width
is x18, if HIGH then it is x9.
This pin provides the Almost-Empty flag status for the queue that has been selected on the output port
for read operations, (selected via RCLK, RDADD and RADEN). This pin is LOW when the selected
queue is almost-empty. This flag output may be duplicated on one of the
PAE
n bus lines. This flag is
synchronized to RCLK.
On the 32Q device the
PAE
n bus is 8 bits wide. This output bus provides
PAE
status of 8 queues
(1 quadrant), within a selected device, having a total of 4 quadrants. During queue read/write operations
these outputs provide programmable empty flag status, in either direct or polled mode. The mode of flag
operation is determned during master reset via the state of the FMinput. This flag bus is capable of
High-Impedance state, this is important during expansion of multi-queue devices. During direct operation
the
PAE
n bus is updated to show the
PAE
status of a quadrant of queues within a selected device.
Selection is made using RCLK, ESTR and RDADD. During Polled operation the
PAE
n bus is loaded with
the
PAE
status of multi-queue flow-control quadrants sequentially based on the rising edge of RCLK.
Output Valid Flag
OW
(1)
(L16)
PAE
(P10)
Output Width
LVTTL
INPUT
LVTTL
OUTPUT
Programmable
Almost-Empty
Flag
PAE
n
(
PAE
7-P11
PAE
6-P12
PAE
5-R12
PAE
4-T12
PAE
3-P13
PAE
2-R13
PAE
1-T13
PAE
0-T14)
PAF
(R8)
Programmable
Almost-Empty
Flag Bus
LVTTL
OUTPUT
Programmable
Almost-Full Flag
LVTTL
OUTPUT
This pin provides the Almost-Full flag status for the queue that has been selected on the input port for
write operations, (selected via WCLK, WRADD and WADEN). This pin is LOW when the selected
queue is almost-full. This flag output may be duplicated on one of the
PAF
n bus lines. This flag is
synchronizedto WCLK.
On the 32Q device the
PAF
n bus is 8 bits wide. At any one time this output bus provides
PAF
status of
8 queues (1 quadrant), within a selected device, having a total of 4 quadrants. During queue read/write
operations these outputs provide programmable full flag status, in either direct or polled mode. The mode
of flag operation is determned during master reset via the state of the FMinput. This flag bus is capable
of High-Impedance state, this is important during expansion of multi-queue devices. During direct
operation the
PAF
n bus is updated to show the
PAF
status of a quadrant of queues within a selected device.
Selection is made using WCLK, FSTR, WRADD and WADEN. During Polled operation the
PAF
n bus
is loaded with the
PAF
status of multi-queue flow-control quadrants sequentially based on the rising of
edge WCLK.
This input is used to provide additional power savings. When the device I/O is setup for HSTL/eHSTL
mode a HIGH on the PD input disables the data inputs on the write port only, providing significant power
savings. In LVTTL mode this pin has no operation
A Partial Reset can be performed on a single queue selected within the multi-queue device. Before a
Partial Reset can be performed on a queue, that queue must be selected on both the write port and read
port 2 clock cycles before the reset is performed. A Partial Reset is then performed by taking
PRS
LOW
for one WCLK cycle and one RCLK cycle. The Partial Reset will only reset the read and write pointers
to the first memory location, none of the devices configuration will be changed.
These are the 18 data output pins. Data is read out of the device via these output pins on the rising edge
of RCLK provided that
REN
is LOW,
OE
is LOW and the queue is selected. Due to bus matching not
all outputs may be used, any unused outputs should not be connected.
The RADEN input is used in conjunction with RCLK and the RDADD address bus to select a queue to
be read from A queue addressed via the RDADD bus is selected on the rising edge of RCLK provided
that RADEN is HIGH. RADEN should be asserted (HIGH) only during a queue change cycle(s). RADEN
should not be permanently tied HIGH.RADEN cannot be HIGH for the same RCLK cycle as ESTR. Note,
PAF
n
(
PAF
7-P7
PAF
6-P6
PAF
5-R6
PAF
4-R7
PAF
3-P5
PAF
2-R5
PAF
1-T5
PAF
0-T4)
PD
(K1)
Programmable
Almost-Full Flag
Bus
LVTTL
OUTPUT
Power Down
HSTL
INPUT
PRS
(T8)
Partial Reset
LVTTL
INPUT
Q[17:0]
Qout (See Pin
table for details)
RADEN
(R14)
Data Output Bus
LVTTL
OUTPUT
Read Address
Enable
LVTTL
INPUT
相關(guān)PDF資料
PDF描述
IDT72T51553L5BB 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION
IDT72T51553L5BBI 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION
IDT72T51553L6BB 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION
IDT72T51553L6BBI 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION
IDT72T51546L5BBI 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
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