參數(shù)資料
型號(hào)： IDT72T51553L5BB
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION
中文描述： 128K X 18 OTHER FIFO, 3.6 ns, PBGA256
封裝： 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256
文件頁數(shù)： 12/57頁
文件大小： 564K
代理商： IDT72T51553L5BB
12
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T51543/72T51553 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
PIN DESCRIPTIONS (CONTINUED)
NOTES:
1. Inputs should not change after Master Reset.
2. These pins are for the JTAG port. Please refer to pages 52-56 and Figures 32-34.
Symbol &
Pin No.
WRADD6-R1
WRADD5-R2
WRADD4-P1
WRADD3-P2
WRADD2-P3
WRADD1-N1
WRADD0-N2)
Name
I/O TYPE
Description
PIN NUMBER TABLE
Symbol
Name
I/O TYPE
Pin Number
D[17:0]
Din
Q[17:0]
Qout
V
CC
V
DDQ
GND
Data Input Bus
HSTL-LVTTL D17-C1, D(16,15)-B(2,1), D(14-12)-A(1-3), D11-B3, D10-A4, D9-B4, D8-C4, D7-A5, D6-B5, D5-C5,
INPUT
D4-A6, D3-B6, D2-C6, D1-A7, D0-B7
Data Output Bus HSTL-LVTTL Q17-C15, Q16-D14, Q(15,14)-A(16,15), Q13-B15, Q12-A14, Q11-B14, Q10-C14, Q9-A13, Q8-B13,
OUTPUT
Q7-C13, Q6-A12, Q5-B12, Q4-C12, Q3-A11, Q2-B11, Q(1,0)-C(11,10)
+2.5V Supply
Power
D(7-10), E(6,7,10,11), F(5,12), G(4,5,12,13), H(4,13), J(4,13), K(4,5,12,13), L(5,12), M(6,7,10,11), N(7-10)
O/P Rail Voltage
Power
D(4-6,11-13), E(4,5,12,13), F(4,13), L(4,13), M(4,5,12,13), N(4-6,11-13)
Ground Pin
Ground
C(2,3), D(1-3), E(1-3,8-9), F(1-3,6-11), G(1-3,6-11), H(1-3,5-12), J(1,3,5-12,14), K(2,6-11,14),
L(6-11,14), M(8-9)
Do Not Connect
None
B16, C16, D(15,16), E(14-16), F(14-16), G(14-16), H(14-16), J(15-16), R9
DNC
WRADD[7:5] are used to select 1 of 8 possible multi-queue devices that may be connected in expansion
mode. These 3 MSB’s will address a device with the matching ID code. The address present on the
WRADD bus will be selected on a rising edge of WCLK provided that WADEN is HIGH, (note, that data
present on the Din bus can be written into the previously selected queue on this WCLK edge and on the
next rising WCLK also, providing that
WEN
is LOW). Two WCLK rising edges after write queue select,
data can be written into the newly selected queue.
The second function of the WRADD bus is to select the quadrant of queues to be loaded on to the
PAF
n
bus during strobed flag mode. The least significant 2 bits, WRADD[1:0] are used to select the quadrant
of a device to be placed on the
PAF
n bus. The most significant 3 bits, WRADD[7:5] are again used
to select 1 of 8 possible multi-queue devices that may be connected in expansion mode. Address bits
WRADD[4:2] are dont care during quadrant selection. The quadrant address present on the WRADD
bus will be selected on the rising edge of WCLK provided that FSTR is HIGH, (note, that data can be written
into the previously selected queue on this WCLK edge). Please refer to Table 1 for details on the WRADD
bus.
These are V
CC
power supply pins and must all be connected to a +2.5V supply rail.
V
CC
(See below)
V
DDQ
(See Pin No.
table for details)
GND
(See below)
Vref
(K3)
+2.5V Supply
Power
O/P Rail Voltage
Power
These pins must be tied to the desired output rail voltage. For LVTTL I/O these pins must be connected
to +2.5V, for HSTL these pins must be connected to +1.5V and for eHSTL these pins must be connected
to +1.8V.
These are Ground pins and must all be connected to the GND supply rail.
Ground Pin
Ground
Reference
Voltage
HSTL
INPUT
This is a Voltage Reference input and must be connected to a voltage level determned fromthe table
"Recommended DC Operating Conditions". The input provides the reference level for HSTL/eHSTL
inputs. For LVTTL I/O mode this input should be tied to GND.
相關(guān)PDF資料
PDF描述
IDT72T51553L5BBI 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION
IDT72T51553L6BB 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION
IDT72T51553L6BBI 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION
IDT72T51546L5BBI 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT72T51546L6BB 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
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