參數(shù)資料
型號(hào)： IDT72T51553L6BB
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION
中文描述： 128K X 18 OTHER FIFO, 3.7 ns, PBGA256
封裝： 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256
文件頁(yè)數(shù)： 11/57頁(yè)
文件大?。?/td> 564K
代理商： IDT72T51553L6BB
11
IDT72T51543/72T51553 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTIONS (CONTINUED)
Symbol &
Pin No.
SENO
(Continued)
SI
(L1)
Name
I/O TYPE
Description
Serial Output
Enable
Serial In
LVTTL
OUTPUT
LVTTL
INPUT
essentially follows the
SENI
input. The user should monitor the
SENO
output of the final device in the chain.
When this output goes LOW, serial loading of all devices has been completed.
During serial programmng this pin is loaded with the serial data that will configure the multi-queue devices.
Data present on SI will be loaded on a rising edge of SCLK provided that
SENI
is LOW. In expansion
mode the serial data input is loaded into the first device in a chain. When that device is loaded and its
SENO
has gone LOW, the data present on SI will be directly output to the SO output. The SO pin of the first device
connects to the SI pin of the second and so on. The multi-queue device setup registers are shift registers.
This output is used in expansion mode and allows serial data to be passed through devices in the chain
to complete programmng of all devices. The SI of a device connects to SO of the previous device in the
chain. The SO of the final device in a chain should not be connected.
Clock input for JTAG function. One of four termnals required by IEEE Standard 1149.1-1990. Test
operations of the device are synchronous to TCK. Data fromTMS and TDI are sampled on the rising
edge of TCK and outputs change on the falling edge of TCK. If the JTAG function is not used this signal
needs to be tied to GND.
One of four termnals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
operation, test data serially loaded via the TDI on the rising edge of TCK to either the Instruction Register,
ID Register and Bypass Register. An internal pull-up resistor forces TDI HIGH if left unconnected.
One of four termnals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
operation, test data serially loaded output via the TDO on the falling edge of TCK fromeither the Instruction
Register, ID Register and Bypass Register. This output is high impedance except when shifting, while
in SHIFT-DR and SHIFT-IR controller states.
TMS is a serial input pin. One of four termnals required by IEEE Standard 1149.1-1990. TMS directs the
device through its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected.
TRST
is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not automatically
reset upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for five TCK
cycles. If the TAP controller is not properly reset then the outputs will always be in high-impedance. If the
JTAGfunction is used but the user does not want to use
TRST
, then
TRST
can be tied with
MRS
to ensure
proper queue operation. If the JTAG function is not used then this signal needs to be tied to GND. An
internal pull-up resistor forces
TRST
HIGH if left unconnected.
The WADEN input is used in conjunction with WCLK and the WRADD address bus to select a queue to
be written in to. A queue addressed via the WRADD bus is selected on the rising edge of WCLK provided
that WADEN is HIGH. WADEN should be asserted (HIGH) only during a queue cycle(s). WADEN should
not be permanently tied HIGH. WADEN cannot be HIGH for the same WCLK cycle as FSTR. Note, that
a write queue selection cannot be made, (WADEN must NOT go active) until programmng of the part has
been completed and
SENO
has gone LOW.
When enabled by
WEN
, the rising edge of WCLK writes data into the selected queue via the input bus,
Din. The queue to be written to is selected via the WRADD address bus and a rising edge of WCLK
while WADEN is HIGH. A rising edge of WCLK in conjunction with FSTR and WRADD will also select
the flag quadrant to be placed on the
PAF
n bus during direct flag operation. During polled flag operation
the
PAF
n bus is cycled with respect to WCLK and the FSYNC signal is synchronized to WCLK. The
PAF
n,
PAF
and
FF
outputs are all synchronized to WCLK. During device expansion the FXO and FXI
signals are based on WCLK. The WCLK must be continuous and free-running.
The
WEN
input enables write operations to a selected queue based on a rising edge of WCLK. A queue
to be written to can be selected via WCLK, WADEN and the WRADD address bus regardless of the state
of
WEN
. Data present on Din can be written to a newly selected queue on the second WCLK cycle after
queue selection provided that
WEN
is LOW. A write enable is not required to cycle the
PAF
n bus (in polled
mode) or to select the
PAF
n quadrant , (in direct mode).
For the 32Q device the WRADD bus is 8 bits. The WRADD bus is a dual purpose address bus. The first
function of WRADD is to select a queue to be written to. The least significant 5 bits of the bus, WRADD[4:0]
are used to address 1 of 32 possible queues within a multi-queue device. The most significant 3 bits,
SO
(M3)
Serial Out
LVTTL
OUTPUT
TCK
(2)
(A8)
JTAG Clock
LVTTL
INPUT
TDI
(2)
(B9)
JTAG Test Data
Input
LVTTL
INPUT
TDO
(2)
(A9)
JTAG Test Data
Output
LVTTL
OUTPUT
TMS
(2)
(B8)
TRST
(2)
(C7)
JTAG Mode
Select
JTAG Reset
LVTTL
INPUT
LVTTL
INPUT
WADEN
(P4)
Write Address
Enable
LVTTL
INPUT
WCLK
(T7)
Write Clock
LVTTL
INPUT
WEN
(T6)
Write Enable
LVTTL
INPUT
WRADD
[7:0]
(WRADD7-T1
Write Address
Bus
LVTTL
INPUT
相關(guān)PDF資料
PDF描述
IDT72T51553L6BBI 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION
IDT72T51546L5BBI 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT72T51546L6BB 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT72T51546L6BBI 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT72T51556 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
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