參數(shù)資料
型號(hào): IDT72T51553L6BB
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION
中文描述: 128K X 18 OTHER FIFO, 3.7 ns, PBGA256
封裝: 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256
文件頁數(shù): 43/57頁
文件大?。?/td> 564K
代理商: IDT72T51553L6BB
43
IDT72T51543/72T51553 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Figure 21. Almost Empty Flag Timing and Queue Switch
Figure 22. Almost Empty Flag Timing
RCLK
RADEN
t
QH
t
QS
t
AH
t
AS
RDADD
D
1
Q
30
t
AH
t
AS
D
1
Q
15
PAE
(Device 1)
t
AELZ
5999 drw25
t
OLZ
t
RAE
t
RAE
t
AEHZ
t
A
D
1
Q
30
W
n
t
A
D
1
Q
30
W
n+1
t
A
D
1
Q
15
W
0
t
A
D
1
Q
15
W
1
REN
t
QH
t
QS
Qout
HIGH-Z
PAE
(Device 2)
HIGH
HIGH-Z
HIGH-Z
*B*
*C*
*E*
*F*
*D*
*A*
*G*
*H*
WCLK
t
ENH
t
CLKH
t
CLKL
WEN
PAE
RCLK
t
ENS
n+1 words in Queue
t
RAE
t
SKEW2
t
RAE
1
2
REN
5999 drw26
t
ENS
t
ENH
n+2 words in Queue
n+1 words in Queue
Cycle:
*A*
Queue 30 of Device 1 is selected on the read port. A queue within Device 2 had previously been selected. The
PAE
flag output and the data outputs of device 1 are High-Impedance.
*B*
No read occurs.
*C*
No read occurs.
*D*
The
PAE
flag output now switches to device 1. Word, Wn is read fromQ30 due to the FWFT operation. This read operation fromQ30 is at the almost empty boundary, therefore
PAE
will go LOW 2 RCLK cycles later.
*E*
Q15 of device 1 is selected.
*F*
The
PAE
flag goes LOW due to the read fromQ30 2 RCLK cycles earlier. Word Wn+1 is read out due to the FWFT operation.
*G*
Word, W0 is read fromQ15 due to the FWFT operation.
*H*
The
PAE
flag goes HIGH to show that Q15 is not almost empty.
NOTE:
1. The waveformhere shows the
PAE
flag operation when no queue switches are occurring and a queue selected on both the write and read ports is being written to then read
fromat the almost empty boundary.
Flag Latencies:
Assertion: 2*RCLK + t
RAE
De-assertion: t
SKEW2
+ RCLK + t
RAE
If t
SKEW2
is violated there will be one extra RCLK cycle.
相關(guān)PDF資料
PDF描述
IDT72T51553L6BBI 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION
IDT72T51546L5BBI 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT72T51546L6BB 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT72T51546L6BBI 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT72T51556 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
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