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參數(shù)資料
| 型號： | IDT72T51553L6BBI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION |
| 中文描述： | 128K X 18 OTHER FIFO, 3.7 ns, PBGA256 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256 |
| 文件頁數(shù)： | 26/57頁 |
| 文件大?。?/td> | 564K |
| 代理商： | IDT72T51553L6BBI |
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26
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T51543/72T51553 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
PAF
n FLAG BUS OPERATION
The IDT72T51543/72T51553 multi-queue flow-control devices can be
configured for up to 32 queues, each queue having its own almost full status.
An active queue has its flag status output to the discrete flags,
FF
and
PAF
, on
the write port. Queues that are not selected for a write operation can have their
PAF
status monitored via the
PAF
n bus. The
PAF
n flag bus is 8 bits wide, so
that 8 queues at a time can have their status output to the bus. If 9 or more queues
are setup within a device then there are 2 methods by which the device can share
the bus between queues, "Direct" mode and "Polled" mode depending on the
state of the FM(Flag Mode) input during a Master Reset. If 8 or less queues
are setup within a device then each will have its own dedicated output fromthe
bus. It is recommended if 8 or less queues are setup in single device mode to
configure the
PAF
n bus to polled mode as it does not require using the write
address (WRADD).
PAF
n - DIRECT BUS
If FMis LOW at master reset then the
PAF
n bus operates in Direct (addressed)
mode. In direct mode the user can address the quadrant of queues they require
to be placed on to the
PAF
n bus. For example, consider the operation of the
PAF
n bus when 26 queues have been setup. To output status of the first
quadrant, Queue[0:7] the WRADD bus is used in conjunction with the FSTR
(
PAF
flag strobe) input and WCLK. The address present on the 2 least significant
bits of the WRADD bus with FSTR HIGH will be selected as the quadrant address
on a rising edge of WCLK. So to address quadrant 1, Queue[0:7] the WRADD
bus should be loaded with “xxxxxx00”, the
PAF
n bus will change status to show
the new quadrant selected 1 WCLK cycle after quadrant selection.
PAF
n[0:7]
gets status of queues, Queue[0:7] respectively.
To address the second quadrant, Queue[8:15], the WRADD address is
“xxxxxx01”.
PAF
n[0:7] gets status of queues, Queue[8:15] respectively. To
address the third quadrant, Queue[16:23], the WRADD address is “xxxxxx10”.
PAF
[0:7] gets status of queues, Queue[16:23] respectively. To address the
fourth quadrant, Queue[24:31], the WRADD address is “xxxxxx11”.
PAF
[0:1]
gets status of queues, Queue[24:25] respectively. Remember, only 26 queues
were setup, so when quadrant 4 is selected the unused outputs
PAF
[2:7] will
be don't care states.
Note, that if a read or write operation is occurring to a specific queue, say
queue x’ on the same cycle as a quadrant switch which will include the queue
‘x’, then there may be an extra WCLK cycle delay before that queues status is
correctly shown on the respective output of the
PAF
n bus. However, the active
PAF
flag will show correct status at all times.
Quadrants can be selected on consecutive clock cycles, that is the quadrant
on the
PAF
n bus can change every WCLK cycle. Also, data present on the input
bus, Din, can be written into a queue on the same WCLK rising edge that a
quadrant is being selected, the only restriction being that a write queue selection
and
PAF
n quadrant selection cannot be made on the same cycle.
If 8 or less queues are setup then queues, Queue[0:7] have their
PAF
status
output on
PAF
[0:7] constantly.
When the multi-queue devices are connected in expansion of more than one
device the
PAF
n busses of all devices are connected together, when switching
between quadrants of different devices the user must utilize the 3 most significant
bits of the WRADD address bus (as well as the 2 LSB’s). These 3 MSB’s
correspond to the device ID inputs, which are the static inputs, ID0, ID1 & ID2.
Please refer to Figure 25
PAF
n - Direct Mode Quadrant Selection
for timng
information. Also refer to Table 1,
Write Address Bus, WRADD
.
PAF
n – POLLED BUS
If FMis HIGH at master reset then the
PAF
n bus operates in Polled (looped)
mode. In polled mode the
PAF
n bus automatically cycles through the 4
quadrants within the device regardless of how many queues have been setup
in the part. Every rising edge of the WCLK causes the next quadrant to be loaded
on the
PAF
n bus. The device configured as the master (MAST input tied HIGH),
will take control of the
PAF
n after
MRS
goes LOW. For the whole WCLK cycle
that the first quadrant is on
PAF
n the FSYNC (
PAF
n bus sync) output will be
HIGH, for all other quadrants, this FSYNC output will be LOW. This FSYNC
output provides the user with a mark with which they can synchronize to the
PAF
n bus, FSYNC is always HIGH for the WCLK cycle that the first quadrant
of a device is present on the
PAF
n bus.
When devices are connected in expansion mode, only one device will be
set as the Master, MAST input tied HIGH, all other devices will have MAST tied
LOW. The master device is the first device to take control of the
PAF
n bus and
will place its first quadrant on the bus on the rising edge of WCLK after the
MRS
input goes HIGH. For the next 3 WCLK cycles the master device will maintain
control of the
PAF
n bus and cycle its quadrants through it, all other devices hold
their
PAF
n outputs in High-Impedance. When the master device has cycled all
of its quadrants it passes a token to the next device in the chain and that device
assumes control of the
PAF
n bus and then cycles its quadrants and so on, the
PAF
n bus control token being passed on fromdevice to device. This token
passing is done via the FXO outputs and FXI inputs of the devices (“
PAF
Expansion Out” and “
PAF
Expansion In”). The FXO output of the master device
connects to the FXI of the second device in the chain and the FXO of the second
connects to the FXI of the third and so on. The final device in a chain has its FXO
connected to the FXI of the first device, so that once the
PAF
n bus has cycled
through all quadrants of all devices, control of the
PAF
n will pass to the master
device again and so on. The FSYNC of each respective device will operate
independently and simply indicate when that respective device has taken control
of the bus and is placing its first quadrant on to the
PAF
n bus.
When operating in single device mode the FXI input must be connected to
the FXO output of the same device. In single device mode a token is still required
to be passed into the device for accessing the
PAF
n bus.
Please refer to Figure 28,
PAF
n Bus – Polled Mode
for timng information.
PAE
n FLAG BUS OPERATION
The IDT72T51543/72T51553 multi-queue flow-control devices can be
configured for up to 32 queues, each queue having its own almost empty status.
An active queue has its flag status output to the discrete flags,
OV
and
PAE
, on
the read port. Queues that are not selected for a read operation can have their
PAE
status monitored via the
PAE
n bus. The
PAE
n flag bus is 8 bits wide, so
that 8 queues at a time can have their status output to the bus. If 9 or more queues
are setup within a device then there are 2 methods by which the device can share
the bus between queues, "Direct" mode and "Polled" mode depending on the
state of the FM(Flag Mode) input during a Master Reset. If 8 or less queues
are setup within a device then each will have its own dedicated output fromthe
bus. It is recommended if 8 or less queues are setup in single device mode to
configure the
PAF
n bus to polled mode as it does not require using the write
address (WRADD).
PAE
n - DIRECT BUS
If FMis LOW at master reset then the
PAE
n bus operates in Direct (addressed)
mode. In direct mode the user can address the quadrant of queues they require
to be placed on to the
PAE
n bus. For example, consider the operation of the
PAE
n bus when 26 queues have been setup. To output status of the first
quadrant, Queue[0:7] the RDADD bus is used in conjunction with the ESTR
(
PAE
flag strobe) input and RCLK. The address present on the 2 least significant
bits of the RDADD bus with ESTR HIGH will be selected as the quadrant address
on a rising edge of RCLK. So to address quadrant 1, Queue[0:7] the RDADD
bus should be loaded with “xxxxxx00”, the
PAE
n bus will change status to show
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72T51546L5BBI | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| IDT72T51546L6BB | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| IDT72T51546L6BBI | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| IDT72T51556 | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| IDT72T51556L5BB | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| IDT72T54242L5BB | 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T54242L6-7BB | 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T54242L6-7BBI | 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T54252L5BB | 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T54252L6-7BB | 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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