參數(shù)資料
型號(hào)： IDT72T51553L6BBI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION
中文描述： 128K X 18 OTHER FIFO, 3.7 ns, PBGA256
封裝： 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256
文件頁(yè)數(shù)： 46/57頁(yè)
文件大?。?/td> 564K
代理商： IDT72T51553L6BBI
46
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T51543/72T51553 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
WCLK
Dn
Prev
PAE
n
RCLK
D5 quad 4
101 xxx11
t
AH
1
t
RAE
D5Quad 4
D5Quad 4
t
PAEHZ
t
PAEZL
xxxx xxx1
xxxx xxx1
t
SKEW3
xxxx xxx0
D5Quad4
2
t
STH
t
PAE
5999 drw30
t
RAE
*DD*
*EE*
*GG*
*FF*
xxxx xxx0
D5Quad4
t
ENH
t
ENS
Wy
D5 Q24
Wy+1
D5 Q24
Wy+3
D5 Q24
Wy+2
D5 Q24
Wa+1
D5 Q17
t
A
t
A
t
A
t
A
t
DH
D3Q8
011 01000
Wn
D5 Q24
Wn+1
D5Q24
D4 quad 3
100 xxx10
*D*
3
*E*
*F*
*G*
t
QH
t
QS
t
AH
t
AS
t
AH
t
AS
t
ENH
t
STH
t
STS
t
ENS
t
ENH
t
RAE
D5 Q24
status
ESTR
RDADD
100 11000
D5Q24
t
AS
t
AH
t
AS
Previous value loaded on to PAE bus
RADEN
t
QH
t
QS
t
STS
Device 5
PAE
*AA*
*BB*
D5 Q17 Status
Bus
PAE
n
Previous value loaded on to PAE bus
REN
Device 5 -Qn
t
A
Wa
D5 Q17
t
DS
WEN
WADEN
FSTR
t
AH
100 11000
t
AS
WRADD
D5Q24
*A*
*B*
1
t
QH
t
QS
t
ENS
Device 5
PAE
n
Wp+1
Wp
Writes to Previous Q
t
DH
t
DS
t
DH
*C*
2
t
QH
t
QS
*H*
Wp+2
t
DS
Wx
D3 Q8
*CC*
3
1
2
3
Figure 26.
PAE
n - Direct Mode, Flag Operation
Cycle:
*A*
Queue 24 of Device 5 is selected for write operations.
Word, Wp is written into the previously selected queue.
*AA*
Queue 24 of Device 5 is selected for read operations.
A quadrant fromanother device has control of the
PAE
n bus.
The discrete
PAE
output of device 5 is currently in High-Impedance and the
PAE
active flag is controlled by the previously selected device.
*B*
Word Wp+1 is written into the previously selected queue.
*BB*
Current Word is kept on the output bus since
REN
is HIGH.
*C*
Word Wp+2 is written into the previously selected queue.
*CC*
Word Wa+1 of D5 Q17 is read due to FWFT.
*D*
Word, Wn is written into the newly selected queue, Q24 of D5. This write will cause the
PAE
flag on the read port to go fromLOW to HIGH (not almost empty) after time,
t
SKEW3
+ RCLK + t
RAE
(if t
SKEW3
is violated one extra RCLK cycle will be added).
*DD*
Word, Wy fromthe newly selected queue, Q24 will be read out due to FWFT operation.
Quadrant 4 of Device 5 is selected on the
PAE
n bus. Q24 of device 5 will therefore have is
PAE
status output on
PAE
[0]. There is a single RCLK cycle latency before
the
PAE
n bus changes to the new selection.
*E*
Queue 8 of Device 3 is selected for write operations.
Word Wn+1 is written into Q24 of D5.
*EE*
Word, Wy+1 is read fromQ24 of D5.
*F*
No writes occur.
*FF*
Word, Wy+2 is read fromQ24 of D5.
The
PAE
n bus changes control to D5, the
PAE
n outputs of D5 go to Low-Impedance and quadrant 4 is placed onto the outputs. The device of the previously selected
quadrant now places its
PAE
n outputs into High-Impedance to prevent bus contention.
The discrete
PAE
flag will go HIGH to show that Q24 of D5 is not almost empty. Q24 of device 5 will have its
PAE
status output on
PAE
[0].
*G*
Quadrant 3 of device 4 is selected on the write port for the
PAF
n bus.
*GG*
The
PAE
n bus updates to show that Q24 of D5 is almost empty based on the reading out of word, Wy+1.
The discrete
PAE
flag goes LOW to show that Q24 of D5 is almost empty based on the reading of Wy+1.
*H*
Word, Wx is written into Q8 of D3.
相關(guān)PDF資料
PDF描述
IDT72T51546L5BBI 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT72T51546L6BB 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT72T51546L6BBI 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT72T51556 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT72T51556L5BB 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
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