參數(shù)資料
型號(hào)： IDT72T51553L6BBI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION
中文描述： 128K X 18 OTHER FIFO, 3.7 ns, PBGA256
封裝： 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256
文件頁(yè)數(shù)： 47/57頁(yè)
文件大?。?/td> 564K
代理商： IDT72T51553L6BBI
47
IDT72T51543/72T51553 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 18 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
RCLK
OE
*G*
W
D - M + 2
D0 Q31
t
A
*I*
t
A
W
0
D6 Q2
*F*
t
QH
t
QS
D0 Q31
111 xxx00
D7 quad 1
110 00010
*D*
*E*
t
AH
t
AS
t
STH
t
STS
D6Q2
W
D-M+1
t
A
W
X +1
Prev. Q
t
OLZ
REN
RADEN
ESTR
WRADD
t
AH
000 11111
t
AS
RDADD
D0Q31
*A*
*B*
000 xxx11
t
QH
t
QS
t
STH
t
STS
5999 drw31
0xxx xxxx
D0Quad4
*BB*
*CC*
*DD*
*EE*
*FF*
t
PAFLZ
1xxx xxxx
D0Quad4
D0Quad4
t
PAF
t
PAF
0xxx xxxx
0xxx xxxx
D0Quad4
1xxx xxxx
D0Quad4
D0Quad4
0xxx xxxx
t
PAFHZ
HIGH-Z
HIGH-Z
t
PAFLZ
t
WAF
*AA*
Device 0
PAF
n
Bus
PAF
n
D
X
Quad y
Prev.
PAF
n
D
X
Quad y
Device 0
PAF
Qout
W
X
Prev. Q
D0 quad4
FSTR
t
A
WCLK
t
SKEW3
2
3
D0 Q31
WEN
t
ENS
t
ENH
WADEN
t
QH
t
QS
t
AH
t
AS
t
AH
t
AS
Din
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
Word W
y
D0 Q31
W
y+1
D0 Q31
W
y+2
D0 Q31
*C*
t
AH
t
AS
*H*
1
HIGH - Z
*GG*
Figure 27.
PAF
n - Direct Mode, Flag Operation
Cycle:
*A*
Queue 31 of device 0 is selected for read operations.
The last word in the output register is available on Qout.
OE
was previously taken LOW so the output bus is in Low-Impedance.
*AA*
Quadrant 4 of device 0 is selected for the
PAF
n bus. The bus is currently providing status of a previously selected quadrant, Quad Y of device X.
*B*
No read operation.
*BB*
Queue 31 of device 0 is selected on the write port.
*C*
Word, Wx+1 is read out fromthe previous queue due to the FWFT effect.
*CC*
PAF
n continues to show status of Quad4 D0.
The
PAF
n bus is updated with the quadrant selected on the previous cycle, D0 Quad 4.
PAF
[7] is LOW showing the status of queue 31.
The
PAF
n outputs of the device previously selected on the
PAF
n bus go to High-Impedance.
*D*
A new quadrant, Quad 1 of Device 7 is selected for the
PAF
n bus.
Word, Wd-m+1 is read fromQ31 D0 due to the FWFT operation. This read is at the
PAF
n boundary of queue D0 Q31. This read will cause the
PAF
[7] output to go from
LOW to HIGH (almost full to not almost full), after a delay t
SKEW3
+ WCLK + tPAF. If t
SKEW3
is violated add an extra WCLK cycle.
*DD*
No write operation.
*E*
No read operations occur,
REN
is HIGH.
*EE*
PAF
[7] goes HIGH to show that D0 Q31 is not almost empty due to the read on cycle *C*
The active queue
PAF
flag of device 0 goes fromHigh-Impedance to Low-Impedance.
Word, Wy is written into D0 Q31.
*F*
Queue 2 of Device 6 is selected for read operations.
*FF*
Word, Wy+1 is written into D0 Q31.
*G*
Word, Wd-m+2 is read out due to FWFT operation.
*GG*
PAF
[7] and the discrete
PAF
flag go LOW to show the write on cycle *DD*causes Q31 of D0 to again go almost full.
Word, Wy+2 is written into D0 Q31.
*H*
No read operation.
*I*
Word, W0 is read fromQ0 of D6, selected on cycle *F* due to FWFT.
相關(guān)PDF資料
PDF描述
IDT72T51546L5BBI 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT72T51546L6BB 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT72T51546L6BBI 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT72T51556 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT72T51556L5BB 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
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