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參數(shù)資料
| 型號： | IDT72T51556L5BB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| 中文描述： | 64K X 36 OTHER FIFO, 3.6 ns, PBGA256 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256 |
| 文件頁數(shù)： | 30/64頁 |
| 文件大小： | 639K |
| 代理商： | IDT72T51556L5BB |
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30
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
Quadrants can be selected on consecutive clock cycles, that is the quadrant
on the
PAE
n/
PR
n bus can change every RCLK cycle. Also, data can be read
out of a Queue on the same RCLK rising edge that a quadrant is being selected,
the only restriction being that a read queue selection and
PAE
n/
PR
n quadrant
selection cannot be made on the same RCLK cycle.
If 8 or less queues are setup then queues, Queue[0:7] have their
PAE
/
PR
status output on
PAE
[0:7] constantly.
When the multi-queue devices are connected in expansion of more than one
device the
PAE
n/
PR
n busses of all devices are connected together, when
switching between quadrants of different devices the user must utilize the 3 most
significant bits of the RDADD address bus (as well as the 2 LSB’s). These 3
MSB’s correspond to the device ID inputs, which are the static inputs, ID0, ID1
& ID2.
Please refer to Figure 28,
PAE
n/
PR
n - Direct Mode Quadrant Selection
for
timng information. Also refer to Table 2,
Read Address Bus, RDADD
.
PAE
n – POLLED BUS
If FMis HIGH at master reset then the
PAE
n/
PR
n bus operates in Polled
(looped) mode. In polled mode the
PAE
n/
PR
n bus automatically cycles through
the 4 quadrants within the device regardless of how many queues have been
setup in the part. Every rising edge of the RCLK causes the next quadrant to
be loaded on the
PAE
n/
PR
n bus. The device configured as the master (MAST
input tied HIGH), will take control of the
PAE
n/
PR
n after
MRS
goes LOW. For
the whole RCLK cycle that the first quadrant is on
PAE
n/
PR
n the ESYNC (
PAE
n/
PR
n bus sync) output will be HIGH, for all other quadrants, this ESYNC output
will be LOW. This ESYNC output provides the user with a mark with which they
can synchronize to the
PAE
n/
PR
n bus, ESYNC is always HIGH for the RCLK
cycle that the first quadrant of a device is present on the
PAE
n/
PR
n bus.
When devices are connected in expansion mode, only one device will be
set as the Master, MAST input tied HIGH, all other devices will have MAST tied
LOW. The master device is the first device to take control of the
PAE
n/
PR
n bus
and will place its first quadrant on the bus on the rising edge of RCLK after the
MRS
input goes LOW. For the next 3 RCLK cycles the master device will maintain
control of the
PAE
n/
PR
n bus and cycle its quadrants through it, all other devices
hold their
PAE
n/
PR
n outputs in High-Impedance. When the master device has
cycled all of its quadrants it passes a token to the next device in the chain and
that device assumes control of the
PAE
n/
PR
n bus and then cycles its quadrants
and so on, the
PAE
n/
PR
n bus control token being passed on fromdevice to
device. This token passing is done via the EXO outputs and EXI inputs of the
devices (“
PAE
Expansion Out” and “
PAE
Expansion In”). The EXO output of
the master device connects to the EXI of the second device in the chain and the
EXO of the second connects to the EXI of the third and so on. The final device
in a chain has its EXO connected to the EXI of the first device, so that once the
PAE
n/
PR
n bus has cycled through all quadrants of all devices, control of the
PAE
n/
PR
n will pass to the master device again and so on. The ESYNC of each
respective device will operate independently and simply indicate when that
respective device has taken control of the bus and is placing its first quadrant
on to the
PAE
n/
PR
n bus.
When operating in single device mode the EXI input must be connected to
the EXO output of the same device. In single device mode a token is still required
to be passed into the device for accessing the
PAE
n bus.
Please refer to Figure 33,
PAE
n/
PR
n Bus – Polled Mode
for timng information.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72T51556L5BBI | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| IDT72T51556L6BB | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| IDT72T51556L6BBI | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| IDT72T51546 | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| IDT72T51546L5BB | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
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| IDT72T54242L6-7BB | 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T54242L6-7BBI | 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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