參數(shù)資料
型號(hào)： IDT72T51556L6BB
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
中文描述： 64K X 36 OTHER FIFO, 3.7 ns, PBGA256
封裝： 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256
文件頁數(shù)： 11/64頁
文件大?。?/td> 639K
代理商： IDT72T51556L6BB
11
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTIONS (CONTINUED)
REN
(T11)
Read Enable
HSTL-LVTTL The
REN
input enables read operations froma selected Queue based on a rising edge of RCLK.
INPUT
A queue to be read fromcan be selected via RCLK, RADEN and the RDADD address bus regardless
of the state of
REN
. Data froma newly selected queue will be available on the Qout output bus on the second
RCLK cycle after queue selection regardless of
REN
due to the FWFT operation. A read enable is not
required to cycle the
PAE
n/
PR
n bus (in polled mode) or to select the
PAE
n quadrant , (in direct mode).
HSTL-LVTTL If serial programmng of the multi-queue device has been selected during master reset, the SCLK input
INPUT
clocks the serial data through the multi-queue device. Data setup on the SI input is loaded into the device
on the rising edge of SCLK provided that
SENI
is enabled, LOW. When expansion of devices is performed
the SCLK of all devices should be connected to the same source.
HSTL-LVTTL During serial programmng of a multi-queue device, data loaded onto the SI input will be clocked into the
INPUT
part (via a rising edge of SCLK), provided the
SENI
input of that device is LOW. If multiple devices are
cascaded, the
SENI
input should be connected to the
SENO
output of the previous device. So when serial
loading of a given device is complete, its
SENO
output goes LOW, allowing the next device in the chain
to be programmed (
SENO
will follow
SENI
of a given device once that device is programmed). The
SENI
input of the master device (or single device), should be controlled by the user.
HSTL-LVTTL This output is used to indicate that serial programmng or default programmng of the multi-queue device
OUTPUT
has been completed.
SENO
follows
SENI
once programmng of a device is complete. Therefore,
SENO
will go LOW after programmng provided
SENI
is LOW, once
SENI
is taken HIGH again,
SENO
will also
go HIGH. When the
SENO
output goes LOW, the device is ready to begin normal read/write operations.
If multiple devices are cascaded and serial programmng of the devices will be used, the
SENO
output
should be connected to the
SENI
input of the next device in the chain. When serial programmng of the
first device is complete,
SENO
will go LOW, thereby taking the
SENI
input of the next device LOW and
so on throughout the chain. When a given device in the chain is fully programmed the
SENO
output
essentially follows the
SENI
input. The user should monitor the
SENO
output of the final device in the chain.
When this output goes LOW, serial loading of all devices has been completed.
HSTL-LVTTL During serial programmng this pin is loaded with the serial data that will configure the multi-queue devices.
INPUT
Data present on SI will be loaded on a rising edge of SCLK provided that
SENI
is LOW. In expansion
mode the serial data input is loaded into the first device in a chain. When that device is loaded and its
SENO
has gone LOW, the data present on SI will be directly output to the SO output. The SO pin of the first device
connects to the SI pin of the second and so on. The multi-queue device setup registers are shift registers.
HSTL-LVTTL This output is used in expansion mode and allows serial data to be passed through devices in the chain
OUTPUT
to complete programmng of all devices. The SI of a device connects to SO of the previous device in the
chain. The SO of the final device in a chain should not be connected.
LVTTL
Clock input for JTAG function. One of four termnals required by IEEE Standard 1149.1-1990. Test
INPUT
operations of the device are synchronous to TCK. Data fromTMS and TDI are sampled on the rising edge
of TCK and outputs change on the falling edge of TCK. If the JTAG function is not used this signal needs
to be tied to GND.
LVTTL
One of four termnals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation,
INPUT
test data serially loaded via the TDI on the rising edge of TCK to either the Instruction Register, ID Register
and Bypass Register. An internal pull-up resistor forces TDI HIGH if left unconnected.
LVTTL
One of four termnals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
OUTPUT
operation, test data serially loaded output via the TDO on the falling edge of TCK fromeither the Instruction
Register, ID Register and Bypass Register. This output is high impedance except when shifting, while in
SHIFT-DR and SHIFT-IR controller states.
LVTTL
TMS is a serial input pin. One of four termnals required by IEEE Standard 1149.1-1990. TMS directs the
INPUT
device through its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected.
LVTTL
TRST
is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not automatically
INPUT
reset upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for five TCK cycles.
If the TAP controller is not properly reset then the outputs will always be in high-impedance. If the JTAG
function is used but the user does not want to use
TRST
, then
TRST
can be tied with
MRS
to ensure
SCLK
(N3)
Serial Clock
SENI
(M2)
Serial Input
Enable
SENO
(M1)
Serial Output
Enable
SI
(L1)
Serial In
SO
(M3)
Serial Out
TCK
(2)
(A8)
JTAG Clock
TDI
(2)
(B9)
JTAG Test Data
Input
TDO
(2)
(A9)
JTAG Test Data
Output
TMS
(2)
(B8)
TRST
(2)
(C7)
JTAG Mode
Select
JTAG Reset
Symbol &
Pin No.
Name
I/O TYPE
Description
相關(guān)PDF資料
PDF描述
IDT72T51556L6BBI 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT72T51546 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT72T51546L5BB 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
IDT74ALVCH16501 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS AND BUS-HOLD
IDT74H16501PA 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS AND BUS-HOLD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT72T54242L5BB 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T54242L6-7BB 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T54242L6-7BBI 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T54252L5BB 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T54252L6-7BB 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*