- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379210 > IDT72T51556L6BB (INTEGRATED DEVICE TECHNOLOGY INC) 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits PDF資料下載
參數(shù)資料
| 型號(hào)： | IDT72T51556L6BB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| 中文描述： | 64K X 36 OTHER FIFO, 3.7 ns, PBGA256 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256 |
| 文件頁數(shù)： | 20/64頁 |
| 文件大?。?/td> | 639K |
| 代理商： | IDT72T51556L6BB |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當(dāng)前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
20
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
SENO
output of a device going fromHIGH to LOW. Note, that
SENI
must be
held LOW when a device is setup for default programmng mode.
When multi-queue devices are connected in expansion mode, the
SENI
of
the first device in a chain can be held LOW. The
SENO
of a device should
connect to the
SENI
of the next device in the chain. The
SENO
of the final device
is used to indicate that default programmng of all devices is complete. When the
final
SENO
goes LOW normal operations may begin. Again, all devices will be
programmed with their maximumnumber of queues and the memory divided
equally between them Please refer to Figure 9,
Default Programmng
.
READING AND WRITING TO THE IDT MULTI-QUEUE
FLOW-CONTROL DEVICE
The IDT72T51546/72T51556 multi-queue flow-control devices can be
configured in two distinct modes, namely Standard Mode and Packet Mode.
STANDARD MODE OPERATION (PKT = LOW ON MASTER RESET)
WRITE QUEUE SELECTION AND WRITE OPERATION
(STANDARD MODE)
The IDT72T51546/72T51556 multi-queue flow-control devices can be
configured up to a maximumof 32 queues into which data can be written via
a common write port using the data inputs (Din), write clock (WCLK) and write
enable (
WEN
). The queue to be written is selected by the address present on
the write address bus (WRADD) during a rising edge on WCLK while write
address enable (WADEN) is HIGH. The state of
WEN
does not impact the queue
selection. The queue selection requires 1 WCLK cycle. All subsequent data
writes will be to this queue until another queue is selected.
Standard mode operation is defined as individual words will be written to the
device as opposed to Packet Mode where complete packets may be written.
The write port is designed such that 100% bus utilization can be obtained. This
means that data can be written into the device on every WCLK rising edge
including the cycle that a new queue is being addressed.
Changing queues requires a mnimumof 3 WCLK cycles on the write port
(see Figure 10,
Write Queue Select, Write Operation and Full flag Operation
).
WADEN goes high signaling a change of queue (clock cycle “A”). The address
on WRADD at that time determnes the next queue. Data presented during that
cycle (“A”) and the next cycle (“B” and “C”), will be written to the active (old)
queue, provided
WEN
is active LOW. If
WEN
is HIGH (inactive) for these 3 clock
cycles, data will not be written in to the previous queue. The write port discrete
full flag will update to show the full status of the newly selected queue (Q
) at this
last cycle’s rising edge (“C”). Data present on the data input bus (Din), can be
written into the newly selected queue (Q
) on the rising edge of WCLK on the
third cycle (“D”) following a change of queue, provided
WEN
is LOW and the
new queue is not full. If the newly selected queue is full at the point of its selection,
any writes to that queue will be prevented. Data cannot be written into a full
queue.
Refer to Figure 10,
Write Queue Select, Write Operation and Full flag
Operation
, Figure 11,
Write Operations & First Word Fall Through
for timng
diagrams and Figure 12,
Full Flag Timng in Expansion Mode
for timng
diagrams.
TABLE 1 — WRITE ADDRESS BUS, WRADD[7:0]
Operation WCLK WADEN
FSTR
WRADD[7:0]
Write
Queue
Select
1
0
0
1
Device Select
(Compared to
ID0,1,2)
Write Queue Address
(5 bits = 32 Queues)
7
6
5
4 3 2
1 0
7
6
5
4 3 2
1 0
Device Select
(Compared to
ID0,1,2)
X
X
X
Quadrant
Address
PAF
n
Quadrant
Select
Q0 : Q7
→
PAF
0 :
PAF
7
Q8 : Q15
→
PAF
0 :
PAF
7
Q16 : Q23
→
PAF
0 :
PAF
7
Q24 : Q31
→
PAF
0 :
PAF
7
Quadrant
Address
00
01
10
11
Queue Status on
PAF
n Bus
5998 drw05
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72T51556L6BBI | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| IDT72T51546 | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| IDT72T51546L5BB | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| IDT74ALVCH16501 | 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS AND BUS-HOLD |
| IDT74H16501PA | 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS AND BUS-HOLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72T54242L5BB | 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T54242L6-7BB | 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T54242L6-7BBI | 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T54252L5BB | 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T54252L6-7BB | 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。